SI9910_05 Datasheet, PDF (4/6 Pages) Vishay Siliconix – Adaptive Power MOSFET Driver

Si9910
Vishay Siliconix
PIN DESCRIPTION
Pin 1: V_DS
Pin 1 or V_DS is a sense input for the maximum source-drain
voltage limit. Two microseconds after a high transition on input
pin 2, an internal timer enables the V_DS(max) sense circuitry. A
catastrophic overcurrent condition, excessive on-resistance,
or insufficient gate-drive voltage can be sensed by limiting
the maximum voltage drop across the power MOSFET. An
external resistor (R3) is required to protect pin 1 from
overvoltage during the MOSFET “off” condition. Exceeding
V_DS(max) latches the Si9910 “off.” Drive is re-enabled on the
next positive- going input on pin 2. If pin 1 is not used, it must
be connected to pin 6 (V_SS).
Pin 2: INPUT
A non-inverting, Schmidt trigger input controls the state of the
MOSFET gate-drive outputs and enables the protection logic.
When the input is low (v V_IL), V_DD is monitored for an
undervoltage condition (insufficiently charged bootstrap
capacitor). If an undervoltage (v V_DD(min)) condition exists,
the driver will ignore a turn-on input signal. An undervoltage
(v V_DD(min)) condition during an “on” state will not be sensed.
Pin 3: V_DD
V_DD supplies power for the driver’s internal circuitry and
charging current for the power MOSFET’s gate capacitance.
The Si9910 minimizes the internal I_DD in the “on” state
(gate-drive outputs high) allowing a “floating” power supply to
be provided by charge pump or bootstrap techniques.
Pin 4: DRAIN
Drain is an analog input to the internal dv/dt limiting circuitry.
An external capacitor (C1) must be used to protect the input
from exposure to the high-voltage (“off” state) drain and to set
the power MOSFET’s maximum rate of dv/dt. If dv/dt feedback
is not used, pin 4 must be left open.
Pin 5: I_SENSE
I_SENSE in combination with an external resistor (R₁₎
protects the power MOSFET from potentially catastrophic
peak currents. I_SENSE is an analog feedback that limits current
during the power MOSFET’s transition to an “on” state. It is
intended to protect power MOSFETs (in a half-bridge
arrangement) from “shoot-through” current, resulting from
excess di/dt and t_rr of flyback diodes or from logic timing
overlap. An 0.8-V drop across (R1) should indicate a current
level that is approximately four times the maximum allowable
load current. When the I_SENSE input is not used, it should be
tied to pin 6 (V_SS).
Pin 6: V_SS
V_SS is the driver’s ground return pin. The applications diagram
illustrates the connection of V_SS for source-referenced
www.vishay.com
4
“floating” applications (half-bridge, high-side) and
ground-referenced applications (half-bridge, low-side).
Pin 7: PULL-DOWN
Pin 8: PULL-UP
Pull-up and pull-down outputs collectively provide the power
MOSFET gate with charging and discharging currents. Turn
“on” or “off” di/dt can be limited by adding resistance (R₂) in
series with the appropriate output.
APPLICATIONS
“Floating” High-Side Drive Applications
As demonstrated in Figure 1, the Si9910 is intended for use
as both a ground-referenced gate driver and as a “high-side”
or source-referenced gate driver in half-bridge applications.
Several features of the Si9910 permit its use in half-bridge
high-side drive applications.
A simple and inexpensive method of isolating a floating supply
to power the Si9910 in high-side driver applications had to be
provided. Therefore, the Si9910 was designed to be
compatible with two of the most commonly used floating
supply techniques: the bootstrap and the charge pump. Both
of these techniques have limitations when used alone. A
properly designed bootstrap circuit can provide
low-impedance drive which minimizes transition losses and
the charge pump circuit provides static operation.
The Si9910 is configured to take advantage of either floating
supply technique if the application is not sensitive to their
particular limitations, or both techniques if switching losses
must be minimized and static operation is necessary. The
schematic above illustrates both the charge pump and
bootstrap circuits used in conjunction with an Si9910 in a
high-side driver application.
Input signal level shifting is accomplished with a passive
pull-up (R4) and n-channel MOSFET (Q2) for pull-down in
applications below 500 V. Total node capacitance defines the
value of R4 needed to guarantee an input transition rate which
safely exceeds the maximum dv/dt rate of the output
half-bridge. Using level-shift devices with higher current
capabilities may necessitate the addition of current-limiting
components such as R5.
Bootstrap Undervoltage Lockout
When using a bootstrap capacitor as a high-side floating
supply, care must be taken to ensure time is available to
recharge the bootstrap capacitor prior to turn-on of the
high-side MOSFET. As a catastrophic protection against
abnormal conditions such as start-up, loss of power, etc., an
internal voltage monitor has been included which monitors the
bootstrap voltage when the Si9910 is in the low state. The
Si9910 will not respond to a high input signal until the voltage
on the bootstrap capacitor is sufficient to fully enhance the
power MOSFET gate. For more details, please refer to
Application Note AN705.
Document Number: 70009
S-42043—Rev. H, 15-Nov-04