SI9241AEY Datasheet, PDF (4/5 Pages) Vishay Siliconix – Single-Ended Bus Transcei

Si9241AEY
Vishay Siliconix
PIN CONFIGURATION
V_DD
TX
CS
FAULT
Narrow Body
SO Package
1
8
2
7
3
6
4
5
RX
V_BAT
K
GND
Top View
ORDERING INFORMATION
Part Number
Temperature Range
Si9241AEY-T1
Si9241AEY-T1—E3 (Lead (Pb)-Free)
−40 to 125_C
PIN DESCRIPTION
Pin Number Symbol
Description
1
V_DD
Positive Power Supply
2
TX
Transmit, Input
3
CS
Chip Select, Input
4
FAULT
Fault, Open Drain Output
5
GND
Ground Connection
6
K
Transmit/Receive, Bidirectional
7
V_BAT
Battery Power Supply
8
RX
Receiver, Output
FUNCTIONAL DESCRIPTION
The Si9241AEY can be either in transmit or receive mode and
it contains over temperature, and short circuit V_BAT fault
detection circuits.
The voltage on K is internally compared to V_BAT/2. If the
voltage on the K pin is less than V_BAT/2 then RX output will be
“low.” If the voltage on the K pin is greater than V_BAT/2 then RX
output will be “high.”
In order to be in transmit mode, CS must be set “low.” When
CS and TX are set “low” the internal MOSFET will turn on,
causing the K pin to be “low.” In the transmit mode, the
processor monitors RX and TX. When the two mirror each
other there is no fault. In the event of over temperature, or short
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circuit to V_BAT, the Si9241AEY will turn off the K output to
protect the IC and the external open drain FAULT pin will be
asserted. The K pin will stay in high impedance and RX will
follow the K pin. The fault will be reset when CS is toggled high.
RX, CS and TX pins have an internal pull up resistor to V_DD
while the K pin has internal pull down resistors. When any one
of the TX, V_BAT or GND pins is open the K output is off.
When CS is set “high” the Si9241AEY is in receive mode and
the internal MOSFET for the K pin is turned off. The RX output
will follow the K pin. If CS is “low” while the IC is receiving data,
an incorrect fault signal will occur.
To inhibit the short detect, tie CS and TX together.
Document Number: 70787
S-40137—Rev. E, 16-Feb-04