IRF840 Datasheet, PDF (4/8 Pages) Motorola, Inc – N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR

IRF840, SiHF840
Vishay Siliconix
2500
2000
1500
V_GS = 0 V, f = 1 MHz
C_iss = C_gs + C_gd, C_ds Shorted
C_rss = C_gd
C_oss = C_ds + C_gd
C_iss
1000
500
C_oss
C_rss
0
10⁰
91070_05
10¹
V_DS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
150 °C
10¹
25 °C
10⁰
0.4
91070_07
V_GS = 0 V
0.6
0.8
1.0
1.2
1.4
V_SD, Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
20
I_D = 8.0 A
16
V_DS = 400 V
V_DS = 250 V
12
V_DS = 100 V
8
4
0
0
91070_06
For test circuit
see figure 13
15
30
45
60
75
Q_G, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Drain-to-Source Voltage
10²
Operation in this area limited
5
by R_DS(on)
2
10 µs
10
100 µs
5
2
1
5
2
0.1
0.1 ²
91070_08
1 ms
10 ms
5
2
1
T_C = 25 °C
T_J = 150 °C
Single Pulse
5 ₁₀ 2 5 ₁₀₂ 2
5 ₁₀₃ 2
V_DS, Drain-to-Source Voltage (V)
5 ₁₀₄
Fig. 8 - Maximum Safe Operating Area
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4
Document Number: 91070
S-81290-Rev. B, 16-Jun-08