SI9110_11 Datasheet, PDF (3/9 Pages) Vishay Siliconix – High-Voltage Switchmode Controllers

Si9110, Si9111
Vishay Siliconix
SPECIFICATIONS^a
Parameter
Symbol
Test Conditions
Unless Otherwise Specified
DISCHARGE = - V_IN = 0 V
V_CC = 10 V, + V_IN = 48 V
R_BIAS = 390 k, R_OSC = 330 k
D Suffix
- 40 °C to 85 °C
Temp.^b Min.^d Typ.^c Max.^d
Error Amplifier
Feedback Input Voltage
V_FB
FB Tied to COMP
Si9110 Room 3.96 4.00 4.04
OSC IN = - V_IN, (OSC Disabled) _{Si9111 Room 3.60 4.00 4.40}
Input BIAS Current
Input OFFSET Voltage
Open Loop Voltage Gain^e
Unity Gain Bandwidth^e
Dynamic Output Impedance^e
Output Current
Power Supply Rejection
Current Limit
I_FB
V_OS
A_VOL
BW
Z_OUT
I_OUT
PSRR
OSC IN = - V_IN, V_FB = 4 V
OSC IN = - V_IN
(OSC Disabled)
Source (V_FB = 3.4 V)
Sink (V_FB = 4.5 V)
9.5 V  V_CC  13.5 V
Room
Room
Room
Room
Room
Room
Room
Room
60
1
0.12
50
25
± 15
80
1.3
1000
- 2.0
0.15
70
500
± 40
2000
- 1.4
Threshold Voltage
Delay to Output^e
Pre-Regulator/Start-Up
V_SOURCE
t_d
V_FB = 0
V_SENSE = 1.5 V, See Figure 1
Room 1.0
1.2
1.4
Room
100 150
Input Voltage
Input Leakage Current
Pre-Regulator Start-Up Current
V_CC Pre-Regulator Turn-Off
Threshold Voltage
+ V_IN
+ I_IN
I_START
V_REG
I_IN = 10 µA
V_CC  9.4 V
Pulse Width  300 µs, V_CC = V_ULVO
I_{PRE-REGULATOR} = 10 µA
Room 120
Room
10
Room
8
15
Room 7.8
8.6
9.4
Undervoltage Lockout
V_REG - V_UVLO
Supply
V_UVLO
V_DELTA
Room 7.0
8.1
8.9
Room 0.3
0.6
Supply Current
Bias Current
Logic
I_CC
I_BIAS
V_LOAD  75 pF (Pin 4)
Room 0.45 0.6
1.0
Room 10
15
20
SHUTDOWN Delay^e
t_SD
SHUTDOWN Pulse Width^e
t_SW
RESET Pulse Width^e
t_RW
Latching Pulse Width
SHUTDOWN and RESET Low^e
t_LW
Input Low Voltage
V_IL
Input High Voltage
V_IH
Input Current Input Voltage High
I_IH
Input Current Input Voltage Low
I_IL
Output
C_L = 500 pF, V_SENSE = - V_IN, See Figure 2 Room
See Figure 3
Room 50
Room 50
50
100
See Figure 3
Room 25
V_IN = 10 V
V_IN = 0 V
Room
2.0
Room 8.0
Room
1
5
Room - 35 - 25
Output High Voltage
V_OH
I_OUT = - 10 mA
Room 9.7
Full
9.5
Output Low Voltage
V_OL
I_OUT = 10 mA
Room
Full
Output Resistance
R_OUT
I_OUT = 10 mA, Source or Sink
Room
Full
Rise Time^e
Fall Time^e
t_r
t_f
C_L = 500 pF
Room
Room
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f. C_STRAY Pin 8 =  5 pF.
0.30
0.50
20
30
25
50
40
75
40
75
Unit
V
nA
mV
dB
MHz

mA
dB
V
ns
V
µA
mA
V
mA
µA
ns
V
µA
V

ns
Document Number: 70004
www.vishay.com
S11-0975-Rev. I, 16-May-11
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000