SI4728CY Datasheet, PDF (3/9 Pages) Vishay Siliconix – N-Channel Synchronous MOSFETs with Break-Before-Make

Si4728CY
Vishay Siliconix
SPECIFICATIONS
Parameter
Power Supplies
Symbol
Test Conditions Unless Specified
T_J = 25_C
4.5 V < V_DD < 5.5 V, 4.5 V < V_D1 < 30 V
Min
Limits
Typ
Max
Logic Voltage
Logic Current
Logic Input
V_DD
I_DD(EN)
I_DD(DIS)
V_DD = 4.5 V, V_IN = 4.5 V
V_DD = 4.5 V, V_IN = 0 V
4.5
5.5
280
500
220
500
High
V_IH
Logic Input Voltage (V_IN)
Low
V_IL
Protection
V_DD = 4.5 V
3.15
2.3
- 0.3
2.25
0.8
Break-Before-Make Reference
Undervoltage Lockout
Undervoltage Lockout Hysteresis
MOSFET Drivers
V_BBM
V_UVLO
V_H
V_DD = 5.5 V
SYNC = 4.5 V
2.4
3.75
4
4.25
0.4
Driver Impedance
MOSFETs
R_DR1
Driver 1
3.6
R_DR2
V_DD = 4.5 V
Driver 2
2
Drain-Source Voltage
Drain-Source On-State Resistance^a
V_DS
r_DS(on)1
r_DS(on)2
I_D = 250 mA
V_DD = 4.5 V, I_D = 10 A
Q1
T_J = 25_C
Q2
30
13
18
8
10.5
Diode Forward Voltage^a
V_SD1
Q1
V_SD2
I_S = 2 A, V_GS = 0 V
Q2
0.7
1.1
0.7
1.1
Dynamic^b (Unless Specified—F_s = 250 kHz, dc = 10%. V_DD = 5 V, I = 10 A, Refer to Switching Test Setup)
Rise Time
t_rdr1
Driver 1
10% - 90%
t_rdr2
Driver 2
31
60
23
40
Fall Time
Turn-Off Delay
Dt
Rise Time
Fall Time
Source-Drain Reverse Recovery
Time—Q₂
t_fdr1
t_fdr2
t_d(off)1
t_d(off)2
Dt_{1 - 2}
Dt_{2 - 1}
t_r
t_f
t_fr2
90% - 10%
See Timing Diagram
10% - 90%
90% - 10%
Driver 1
Driver 2
V_IN to G₁
V_IN to G₂
G₁ to G₂
G₂ to G₁
S₁/D₂
S₁/D₂
I_F 2.7 A, di/dt = 100 A/ms
9
20
15
40
50
100
27
60
19
40
38
80
29
60
10
20
50
80
Notes
a. Pulse test: pulse width v300 ms; duty cycle v 2%.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Unit
V
mA
V
V
W
V
mW
V
ns
Document Number: 71286
S-03075—Rev. C, 03-Feb-03
www.vishay.com
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