DG4051E Datasheet, PDF (3/20 Pages) Vishay Siliconix – Low Capacitance, Low Charge Injection, 4- / 8-Channel, Triple SPDT, Analog Multiplexers

www.vishay.com
DG4051E, DG4052E, DG4053E
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (T_A = 25 °C, unless otherwise noted)
PARAMETER
LIMIT
UNIT
V+ to V-
GND to V-
Digital Inputs ^a, V_S, V_D
-0.3 to +18
-18
V
(V-) - 0.3 to (V+) + 0.3
or 30 mA, whichever occurs first
Continuous Current (any terminal)
Peak Current, S or D (pulsed 1 ms, 10 % duty cycle)
30
mA
100
Storage Temperature
16-pin TSSOP ^c
Power Dissipation ^b
16-pin miniQFN ^{d, f}
16-pin narrow SOIC ^e
16-pin TSSOP ^c
Thermal Resistance ^b
16-pin miniQFN ^{d, f}
16-pin narrow SOIC ^e
ESD Human Body Model (HBM); per ANSI / ESDA / JEDEC^® JS-001
Latch Up Current, per JESD78D
-65 to +150
450
525
640
178
152
125
2500
400
°C
mW
°C/W
V
mA
Notes
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 5.6 mW/°C above 70 °C.
d. Derate 6.6 mW/°C above 70 °C.
e. Derate 8.0 mW/°C above 70 °C.
f. Manual soldering with iron is not recommended for leadless components. The miniQFN-16 is a leadless package. The end of the lead
terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip
cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS FOR DUAL SUPPLIES
PARAMETER
SYMBOL
Analog Switch
Analog Signal Range ^e V_ANALOG
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
V+ = 5 V, V- = -5 V
V_{IN(A, B, C, and enable)} = 2 V, 0.8 V ^a
On-Resistance
R_ON
I_S = 1 mA, V_D = -3 V, 0 V, 3 V
On-Resistance Match R_ON
I_S = 1 mA, V_D = ± 3 V
On-Resistance
Flatness
R_FLATNESS
I_S = 1 mA, V_D = -3 V, 0 V, 3 V
Switch Off
Leakage Current
I_S(off)
I_D(off)
V+ = 5.5 V, V- = -5.5 V,
V_D = ± 4.5 V, V_S =  4.5 V
Channel On
Leakage Current
Digital Control
Input Current, V_IN Low
Input Current, V_IN High
Input Capacitance ^e
I_D(on)
I_IL
I_IH
C_IN
V+ = 5.5 V, V- = -5.5 V,
V_S = V_D = ± 4.5 V
V_{IN(A, B, C, and enable)} under test = 0.6 V
V_{IN(A, B, C, and enable)} under test = 2 V
f = 1 MHz
TEMP. ^b
Full
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Full
Full
Room
-40 °C to +125 °C -40 °C to +85 °C
TYP. ^c
UNIT
MIN. ^d MAX. ^d MIN. ^d MAX. ^d
-
-5
5
-5
5
V
68
-
78
-
78
-
-
106
-
97
0.91
-
6
-
6

-
-
6
-
6
10
-
17
-
17
-
-
20
-
19
± 0.05 -1
1
-1
1
-
-50
50
-5
5
± 0.05 -1
1
-1
1
nA
-
-50
50
-5
5
± 0.05 -1
1
-1
1
-
-50
50
-5
5
0.02 -1
1
-1
1
μA
0.02 -1
1
-1
1
3.4
-
-
-
-
pF
S16-0623-Rev. A, 11-Apr-16
3
Document Number: 69685
For technical questions, contact: [e-mail]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000