AN105 Datasheet, PDF (3/7 Pages) Vishay Siliconix – FETS AS VOLTAGE-CONTROLLED RESISTORS

AN105
+V
Reducing Signal Distortion
0
The majority of VCR applications require that signal
distortion be kept to a minimum. Also, numerous
–V
R
applications require large signal handling capability. A
simple feedback technique may be used to reduce
Diode
distortion while permitting large signal handling
Cathode
capability; a small amount of drain signal is coupled to the
Diode
when Signal
Swings Negative
gate through a resistor divider network, as shown in
V_IN
Anode
G
V_OUT ^{Figure 6.}
–
V_GS
+
VCR
The application of a part of the positive drain signal to the
gate causes the channel depletion layer to decrease, with
a corresponding increase in drain current. Increasing the
drain current for a given drain voltage tends to linearize
Figure 5. Simple Attenuator Circuit
the V_GS bias curves. On the negative half-cycle, a small
negative voltage is coupled to the gate to reduce the
amount of drain-gate forward bias. This in turn reduces
the drain current and linearizes the bias lines. Now the
R₁ ^{VCR Linearization}
channel resistance is dependent on the dc gate control
voltage and not on the drain signal, unless the V_DS = V_GS
– V_GS(off) locus is approached. Resistors R₂ and R₃ in
Figure 6 couple the drain signal to the gate; the resistor
R₂
V_IN
R₃
–
V_GG
+
values are equal, so that symmetrical voltage-current
V_OUT ^{characteristics are produced in both quadrants. The}
resistors must be sufficiently large to provide minimum
VCR
loading to the circuit:
R₂ = R₃ // 10(r_DS//R_load//R₁)
R₂ = R₃ w 10 [R₁ ør_DS (max) øR_L]
(3)
Figure 6.
R₁
R₂
V_CONTROL
V_IN
+
R₃
VCR
Siliconix
10-Mar-97
Figure 7.
Typically, 470-kW resistors will work well for most ap-
plications. R₁ is selected so that the ratio of r_DS(on) øR_L to
[(r_DS(on) øR_L) + R₁] give the desired output voltage, or:
r_DS(on) ø R_L
V_O + V_{I (rDS(on) ø RL) ) R1}
(4)
V_OUT ^{The feedback technique used in Figure 6 requires that the}
gate control voltage, V_GG, be twice as large as V_GS in Fig-
ure 5 for the same r_DS value. Use of a floating supply be-
tween the resistor junction and the FET gate will over-
come this problem. The circuit is shown in Figure 7 and
allows the gate control voltage to be the same value as that
voltage used without a feedback circuit, while preserving
the advantages to be gained through the feedback tech-
nique.
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