AN105 Datasheet, PDF (1/7 Pages) Vishay Siliconix – FETS AS VOLTAGE-CONTROLLED RESISTORS

FETs As VoltageĆControlled Resistors
AN105
Introduction: The Nature of VCRs
A voltage-controlled resistor (VCR) may be defined as a
three-terminal variable resistor where the resistance val-
ue between two of the terminals is controlled by a voltage
potential applied to the third.
For a junction field-effect transistor (JFET) under certain
operating conditions, the resistance of the drain-source
channel is a function of the gate-source voltage alone and
the JFET will behave as an almost pure ohmic resistor.
Maximum drain-source current, I_DSS, and minimum re-
sistance r_DS(on), will exist when the gate-source voltage
is equal to zero volts (V_GS = 0). If the gate voltage is in-
creased (negatively for n-channel JFETs and positively
for p-channel), the resistance will also increase. When the
drain current is reduced to a point where the FET is no
longer conductive, the maximum resistance is reached.
The voltage at this point is referred to as the pinchoff or
cutoff voltage and is symbolized by V_GS = V_GS(off). Thus
the device functions as a voltage- controlled resistor.
V_DS = V_GS - V_GS(off)
Region 1
Ohmic Region
Locus Curve
Region 2
I_DSS ^{VGS = 0}
Current Saturation Region
V_GS t 0
V_GS → V_GS(off)
V_P
V_DS - DrainĆSource Voltage (V)
Figure 1. Typical NĆChannel JFET
Operating Characteristics
Figure 1 details typical operating characteristics of an n-
channel JFET. Most amplification or switching operations
of FETs occur in the constant-current (saturated) region,
shown as Region II. A close inspection of Region I (the un-
saturated or pre-pinchoff area) reveals that the effective
slope indicative of conductance across the channel from
drain-to-source is different for each value of gate-source
bias voltage. The slope is relatively constant over a range of
applied drain voltages, so long as the gate voltage is also
constant and the drain voltage is low.
Resistance Properties of FETs
The unique resistance-controlling properties of FETs can
be deduced from Figure 2, which is an expanded-scale
plot of the encircled area in the lower left-hand corner of
Figure 1. The output characteristics all pass through the
origin, near which they become almost straight lines so
that the incremental value of channel resistance, r_DS, is
essentially the same as that of dc resistance, r_DS, and is a
function of V_GS.
Figure 2 shows an extension of the operating characteris-
tics into the third quadrant for a typical n-channel JFET.
While such devices are normally operated with a positive
drain-source voltage, small negative values of V_DS are
possible. This is because the gate-channel PN junction
must be slightly forward-biased before any significant
amount of gate current flows. The slope of the V_GS bias
line is equal to I_D/V_DS = 1/r_DS. This value is controlled
by the amount of voltage applied to the gate. Minimum
r_DS, usually expressed as r_DS(on), occurs at V_GS = 0 and
is dictated by the geometry of the FET. A device with a
channel of small cross-sectional area will exhibit a high
r_DS(on) and a low I_DSS. Thus a FET with high I_DSS should
be chosen where design requirements indicate the need
for a low r_DS(on).
Updates to this app note may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70598.
Siliconix
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10-Mar-97