U440-E3 Datasheet, PDF (2/7 Pages) Vishay Siliconix – Matched N-Channel JFET Pairs

U440/441
Vishay Siliconix
SPECIFICATIONS (T_A = 25_C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Conditions
Typ^a
Limits
U440
U441
Min Max Min Max
Static
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage
Saturation Drain Current^b
Gate Reverse Current
Gate Operating Current
Gate-Source Forward Voltage
Dynamic
V_(BR)GSS
V_GS(off)
I_DSS
I_GSS
I_G
V_GS(F)
I_G = –1 mA, V_DS = 0 V
V_DS = 10 V, I_D = 1 nA
V_DS = 10 V, V_GS = 0 V
V_GS = –15 V, V_DS = 0 V
T_A = 125_C
V_DG = 10 V, I_D = 5 mA
T_A = 125_C
I_G = 1 mA , V_DS = 0 V
–35 –25
–25
–3.5
–1
–6
–1
–6
15
6
30
6
30
–1
–500
–500
–2
–1
–500
–500
–0.3
0.7
Common-Source
Forward Transconductance
g_fs
Common-Source
Output Conductance
g_os
Common-Source
Input Capacitance
C_iss
Common-Source Reverse
Transfer Capacitance
C_rss
Equivalent Input
Noise Voltage
e_n
V_DS = 10 V, I_D = 5 mA
f = 1 kHz
V_DS = 10 V, I_D = 5 mA
f = 1 MHz
V_DS = 10 V, I_D = 5 mA
f = 10 kHz
6
4.5
9
4.5
9
70
200
200
3
1
4
Matching
Differential Gate-Source Voltage
Gate-Source Voltage
Differential Change
with Temperature
|V_GS1 – V_GS2|
D|V_GS1 – V_GS2|
DT
V_DG = 10 V, I_D = 5 mA
6
10
20
V_DG = 10 V, I_D = 5 mA
T_A = –55 to 125_C
20
Saturation Drain Current Ratio^c
I_DSS1
I_DSS2
V_DS = 10 V, V_GS = 0 V
0.97
Transconductance Ratio^c
g_fs1
g_fs2
V_DS = 10 V, I_D = 5 mA
f = 1 kHz
0.97
Common Mode Rejection Ratio
CMRR
V_DG = 5 to 10 V, I_D = 5 mA
85
Notes
a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
b. Pulse test: PW v300 ms duty cycle v3%.
c. Assumes smaller value in the numerator.
Unit
V
mA
pA
nA
pA
nA
V
mS
mS
pF
nV⁄
√Hz
mV
mV/_C
dB
NZFD
www.vishay.com
8-2
Document Number: 70251
S-04031—Rev. D, 04-Jun-01