DG417BMIL Datasheet, PDF (2/11 Pages) Vishay Siliconix – Precision Monolithic Quad SPST CMOS Analog Switches

www.vishay.com
DG417BMIL, DG418BMIL, DG419BMIL
Vishay Siliconix
ORDERING INFORMATION
PART
CONFIGURATION TEMP. RANGE
DG417B
SPST x 1, NC
PACKAGE
DG418B
SPST x 1, NO - 55 °C to 125 °C 8-pin CerDIP
DG419B
SPDT x 1
ORDERING PART
9073704PA
DG417BAK
DG417BAK-E3
9073705PA
DG418BAK
DG418BAK-E3
9073706PA
DG419BAK
DG419BAK-E3
GENERIC
DG417BAK/883
DG417BAK
DG417BAK-E3
DG418BAK/883
DG418BAK
DG418BAK-E3
DG419BAK/883
DG419BAK
DG419BAK-E3
DSCC NUMBER
5962-9073704MPA
-
-
5962-9073705MPA
-
-
5962-9073706MPA
-
-
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltages Referenced to V-
V_L
Digital inputs^a, V_S, V_D
Current, (any terminal) continuous
Current (S or D) pulsed at 1 ms, 10 % duty cycle
Storage temperature
Power dissipation (package)^b
V+
GND
8-pin CerDIP^c
LIMIT
44
25
(GND - 0.3) to (V+) + 0.3
(V-) - 2 V to (V+) + 2
or 30 mA, whichever occurs first
30
100
- 65 to 150
600
UNIT
V
mA
°C
mW
Notes
a. Signals on S_X, D_X or IN_X exceeding V + or V - will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 8 mW/°C above 75 °C.
SCHEMATIC DIAGRAM (Typical Channel)
V+
V_L
V_IN
GND
Level
Shift/
Drive
S
V-
V+
D
V-
Fig. 1
S12-0496-Rev. B, 05-Mar-12
2
Document Number: 63275
For technical questions, contact: [e-mail]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000