SI786 Datasheet, PDF (14/14 Pages) Vishay Siliconix – Dual-Output Power-Supply Controller

Si786
Vishay Siliconix
Both minimum capacitance and maximum ESR requirements
must be met. In order to get the low ESR, a capacitance value
of two to three times greater than the required minimum may
be necessary.
The equation for output ripple in continuous current mode is:
V_OUT(RPL) + I_LPP(MAX)
ǒESR_CF ) _ǒ2
1
Pxf
Ǔ
C
Ǔ
F
The equations for capacitive and resistive components of the
ripple in pulse-skipping mode are:
V_OUT(RPL)(C) +
(4)^ǒ10^–4Ǔ(L)
ǒ_RCS2Ǔǒ_CFǓ
ǒ Ǔ 1
V_OUT
)
1
V_IN–V
OUT
V_OUT(RPL)(R)
+
(0.02)^ǒESR_CF^Ǔ
R_CS
The total ripple, V_OUT(RPL) , can be approximated
as follows:
if
then
otherwise,
V_OUT(RPL)(R) < 0.5 V_OUT(RPL)(C),
V_OUT(RPL) = V_OUT(RPL)(C),
V_OUT(RPL) = 0.5 V_OUT(RPL)(C) +
V_OUT(RPL)(R).
Lower Voltage Input
The application circuit shown here can be easily modified to
work with 5.5-V to 12-V input voltages. Oscillation frequency
should be set at 200 kHz and increase the output capacitance
to 660 mF on the 5-V output to maintain stable performance up
to 2 A of load current. Operation on the 3.3-V supply will not be
affected by this reduced input voltage.
www.vishay.com
14
Document Number: 70189
S-40807—Rev. J, 26-Apr-04