SI9130 Datasheet, PDF (13/13 Pages) Vishay Siliconix – Pin-Programmable Dual Controller-Portable PCs

Si9130
Vishay Siliconix
DESIGN CONSIDERATIONS
Inductor Design
Three specifications are required for inductor design: inductance
(L), peak inductor current (I_LPEAK), and coil resistance (R_L). The
equation for computing inductance is:
ǒ Ǔ ǒ Ǔ _{L +} V_OUT V_IN(MAX)–V_OUT
ǒ Ǔ ǒ Ǔ _VIN(MAX) (f) _IOUT (LIR)
Where:
V_OUT = Output voltage (3.3 V or 5 V);
V_IN(MAX) = Maximum input voltage (V);
f = Switching frequency, normally
300 kHz;
I_OUT = Maximum dc load current (A);
LIR = Ratio of inductor pea-to-peak ac current to
average dc load current, typically 0.3.
When LIR is higher, smaller inductance values are acceptable, at
the expense of increased ripple and higher losses.
The peak inductor current (I_LPEAK) is equal to the steady-state
load current (I_OUT) plus one half of the peak-to-peak ac current
(I_LPP). Typically, a designer will select the ac inductor current to be
30% of the steady-state current, which gives I_LPEAK equal to 1.15
times I_OUT.
The equation for computing peak inductor current is:
ǒ Ǔ ǒ Ǔ VOUT VIN(MAX)–VOUT
ILPEAK + IOUT )
ǒ Ǔ (2)(f)(L) VIN(MAX)
OUTPUT CAPACITORS
The output capacitors determine loop stability and ripple voltage
at the output. In order to maintain stability, minimum capacitance
and maximum ESR requirements must be met according to the
following equations:
Document Number: 70190
S-40805—Rev. F, 26-Apr-04
C_F
u
V_REF
ǒ_VOUTǓǒ_RCSǓ_(2)(p)(GPWP)
and,
ESR_CF
t
ǒ_VOUTǓǒ_RCSǓ
V_REF
Where:
C_F = Output filter capacitance (F)
V_REF = Reference voltage, 3.3 V;
V_OUT = Output voltage, 3.3 V or 5 V;
R_CS = Sense resistor (W);
GBWP = Gain-bandwidth product, 60 kHz;
ESR_CF = Output filter capacitor ESR (W).
Both minimum capacitance and maximum ESR requirements
must be met. In order to get the low ESR, a capacitance value two
to three times greater than the required minimum may be
necessary.
The equation for output ripple in continuous current mode is:
ǒ Ǔ V_OUT(RPL) + I_LPP(MAX)
ESR_CF ) ₍₂
1
f CF)
The equations for capacitive and resistive components of the
ripple in pulse-skipping mode are:
V_OUT(RPL)(C) +
(4)^ǒ10^–4Ǔ(L)
ǒ_RCS2Ǔǒ_C
Ǔ
F
ǒ Ǔ 1
V_OUT
)
1
V_IN–V_OUT
Volts
V_OUT(RPL)(R)
+
(0.02)^ǒESR_CF^Ǔ
R_CS
Volts
The total ripple, V_OUT(RPL) , can be approximated
as follows:
if
then
otherwise,
V_OUT(RPL)(R) < 0.5 V_OUT(RPL)(C),
V_OUT(RPL) = V_OUT(RPL)(C),
V_OUT(RPL) = V_OUT(RPL)(C) +
V_OUT(RPL)(R).
Lower Voltage Input
The application circuit shown here can be easily modified to work
with 5.5-V to 12-V input voltages. Oscillation frequency should be
set at 200 kHz and increase the output capacitance to 660 mF on
the 5-V output to maintain stable performance up to 2 A of load
current. Operation on the 3.3-V supply will not be affected by this
reduced input voltage.
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