DG535_08 Datasheet, PDF (11/12 Pages) Vishay Siliconix – 16-Channel Wideband Video Multiplexers

DETAILED DESCRIPTION
Since no PN junctions exist between the signal path and V+,
positive overvoltages are not a problem, unless the
breakdown voltage of the DMOS drain terminal (see Figure
13) (+ 18 V) is exceeded. Positive overvoltage conditions
must not exceed + 18 V with respect to the GND pin. If this
condition is possible (e.g. transients in the signal), then a
diode or Zener clamp may be used to prevent breakdown.
The overvoltage conditions described may exist if the
supplies are collapsed while a signal is present on the inputs.
If this condition is unavoidable, then the necessary steps
outlined above should be taken to protect the device
DC Biasing
To avoid negative overvoltage conditions and subsequent
distortion of ac analog signals, dc biasing may be necessary.
Biasing is not required, however, in applications where
signals are always positive with respect to the GND or
substrate connection, or in applications involving
multiplexing of low level (up to ± 200 mV) signals, where
forward biasing of the PN substrate-source/drain terminals
would not occur.
Biasing can be accomplished in a number of ways, the
simplest of which is a resistive potential divider and a few dc
blocking capacitors as shown in Figure 14.
+ 15 V
Analog
Signal
C₁
+
IN
R₂
100 µF/16 V
Tantalum
R₁
S
V+
DG536
GND
C₂
+
D
Analog
Signal
OUT
100 µF/16 V
Tantalum
DG535/536
Vishay Siliconix
An alternative method is to offset the supply voltages (see
Figure 15).
Decoupling would have to be applied to the negative supply
to ensure that the substrate is well referenced to signal
ground. Again the capacitors should be of a type offering
good high frequency characteristics.
Level shifting of the logic signals may be necessary using
this offset supply arrangement.
Analog
Signal
IN
+ 12 V
V+
S
DG536 ^D
GND
Analog
Signal
OUT
Decoupling
Capacitors
+
-3V
Figure 15. DG536 with Offset Supply
TTL to CMOS level shifting is easily obtained by using a
MC14504B.
Circuit Layout
Good circuit board layout and extensive shielding is essential
for optimizing the high frequency performance of the DG536.
Stray capacitances on the PC board and/or connecting leads
will considerably degrade the ac performance. Hence, signal
paths must be kept as short as practically possible, with
extensive ground planes separating signal tracks.
Figure 14. Simple Bias Circuit
R₁ and R₂ are chosen to suit the appropriate biasing
requirements. For video applications, approximately 3 V of
bias is required for optimal differential gain and phase
performance. Capacitor C₁ blocks the dc bias voltage from
being coupled back to the analog signal source and C₂
blocks the dc bias from the output signal. Both C₁ and C₂
should be tantalum or ceramic disc type capacitors in order
to operate efficiently at high frequencies. Active bias circuits
are recommended if rapid switching time between channels
is required.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?70070.
Document Number: 70070
S-71241–Rev. E, 25-Jun-07
www.vishay.com
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