SI4724CY_05 Datasheet, PDF (1/8 Pages) Vishay Siliconix – N-Channel Synchronous MOSFETs

SPICE Device Model Si4724CY
Vishay Siliconix
N-Channel Synchronous MOSFETs
FUNCTIONAL DESCRIPTION
The SI4724CY is a high-speed driver designed to operate in high
frequency dc-dc switchmode power supplies. It is designed to be
used with any single output PWM IC or ASIC to produce a highly
efficient synchronous rectifier converter.
Under-voltage protection is provided for the Vdd power supply. The
device includes a bootstrap diode, integrated Schottky diode, and fast
switching times.
MODEL DESCRIPTION
The driver circuit was decomposed into elemental blocks, and then
modeled accordingly as per the data sheet and specific topological
IC information provided to AEi Systems by Vishay’s engineers.
IsSpice models for the output MOSFETs, bootstrap PNP diode, and
the Schottky diode were provided and used in the modeling of the
SI4724CY. No efforts were made to improve the models although
they were reviewed and comments are shown below.
Using ICAP/4, a SPICE package from AEi Systems, a model of the
driver was then created using the modules and a corresponding
schematic and netlist was generated.
The model includes the following functionality and features:
• Proper transient response including variations with external
components.
• Proper connectivity as per the real-life part
• Output rise and fall times for varying loads
• Under voltage lockout & hysteresis
• Switching times (turn off and propagation delays)
• Schottky behavior
• Bootstrap voltage and diode characteristics
• Logic input voltage thresholds
• Break-before-make reference
Note: The variation of the V_ref and logic input voltage levels with V_DD are not modeled.
The model operation is described as follows:
• V_DD under voltage lockout and threshold is modeled by S2,
V10, and R5.
• The V_BBM/V_ref, Sync, and V_IN comparisons are handled by B7,
B1, and B_IN, respectively. The logic input threshold value used
was 2.3V. This value is static but could be made a function of
V_IN.
• The RC combinations, R2/C1, R8/C2 and R7/C1 account for
the majority of the IO propagation delays and the T_ON/T_OFF
delay matching.
• The level shifting and the logic functions are modeled by B4 and
B5.
• The output FETs have been modeled to provide the appropriate
drive performance along with the proper values of r_DSon (values
used: G1 n-Channel 0.7 Ω/n-Channel 1.5 Ω, G2 n-Channel 0.5
Ω/n-Channel 1 Ω)
ASSUMPTIONS
• Behavior is based on typical values given in the specification
sheet for operation at 27 ºC.
• Some thermal variations are modeled including some FET
related parameters and the propagation delay and are
represented in the subcircuit.
• The SPICE syntax used is compatible with Intusoft ICAP/4. A
PSpice version of the subcircuit is also provided.
Document Number: 72365
S-50464Rev. B, 14-Mar-05
www.vishay.com
1