DG4051A Datasheet, PDF (1/14 Pages) Vishay Siliconix – 8-Channel, Dual 4-Channel, Triple 2-Channel Multiplexers, with 0.5 pC Charge Injection

New Product
DG4051A/DG4052A/DG4053A
Vishay Siliconix
8-Channel, Dual 4-Channel, Triple 2-Channel
Multiplexers, with 0.5 pC Charge Injection
DESCRIPTION
The DG4051A, DG4052A and DG4053A are precision low
voltage, single and dual supply CMOS analog multiplexers.
The DG4051A is an 8-channel multiplexer, the DG4052A is
a dual 4-channel multiplexer and the DG4053A is a triple
2-channel multiplexer or triple SPDT.
They are designed to operate from a + 2.7 V to + 12 V single
supply or from ± 2.5 V to ± 5 V dual supplies and are fully
specified at + 3 V, + 5 V and ± 5 V. All control logic inputs
have guaranteed 2.0 V high limit when operating from + 5 V
or ± 5 V supplies and 1.4 V when operating from a + 3 V
supply.
The DG4051A, DG4052A and DG4053A switches conduct
equally well in both directions, offer rail to rail analog signal
handling and can be used both as multiplexers as well as
de-multiplexers.
< 0.5 pC low charge injection coupled with very low switch
capacitance make these products ideal for precision
instrumentation multiplexers.
Operating temperature is specified from - 40 °C to + 125 °C.
The DG4051A, DG4052A and DG4053A are available in
16 lead SOIC, TSSOP and the space saving 1.8 x 2.6 mm
miniQFN packages.
FEATURES
• + 2.7 V to + 12 V single supply operation
± 2.5 V to ± 5 V dual supply operation
• Fully specified at + 3 V, + 5 V, ± 5 V
• 100 Ω maximum on-resistance
RoHS
COMPLIANT
• Low voltage, 2.5 V CMOS/TTL compatible
• Low charge injection (< 0.5 pC typ.)
• High bandwidth: 330 MHz to 700 MHz
• Low switch capacitance (C_s(off) 3 pF typ.)
• Excellent isolation and crosstalk performance (typ. 47 dB at
100 MHz)
• 16 pin SOIC, TSSOP and miniQFN package (1.8 x 2.6 mm)
• Fully specified from - 40 °C to + 85 °C and - 40 °C to + 125 °C
APPLICATIONS
• Precision instrumentation
• Sample and hold applications
• Medical instruments
• High speed communication applications
• Automated test equipment
• High-end data acquisition
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG4051A
TSSOP16
DG4052A
TSSOP16
X4 1
X6 2
X3
X7 4
X5 5
ENABLE 6
V_EE
7
GND 8
Logic
Top View
16 VCC
15 X2
14 X1
13 _X0
12 X3
11 A
10 B
9C
Y0 1
Y2 2
Y
3
Y3 4
Y1 5
ENABLE 6
V_EE
7
GND 8
Logic
16 V_CC
15 X2
14 X1
13 X
12 X0
11 X3
10 A
9B
Y1 ¹
Y0 ²
Z1 ³
Z4
Z0 ⁵
EENNABLE 6
V_EE
7
GND 8
Top View
ENABLE = LO, all switches are controlled by addr pins.
ENABLE = HI, all switches are off.
DG4053A
TSSOP16
Top View
16 VCC
15 Y
14 _X
13 X1
12 _X0
11 A
10 B
9C
Document Number: 69828
S-80839-Rev. B, 21-Apr-08
www.vishay.com
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