PI2061 Datasheet, PDF (5/16 Pages) Vicor Corporation – High Side High Voltage Load Disconnect Switch Controller IC

Not Recommended for New Designs
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Functional Description:
The PI2061 Cool-Switch is designed to drive an N-channel
MOSFET in a high side Circuit Breaker application. As
shown in Figure 1, the load current is sensed through the
sense resistor (Rs). At power up the controller has a
higher threshold voltage compared to steady state
operation to allow capacitive load charging without
nuisance tripping of the breaker.
Differential Amplifier:
The PI2061 integrates a high-speed fixed offset voltage
differential amplifier to sense the difference between the
Sense Positive (SP) pin and Sense Negative (SN) pin
voltage with high accuracy. The amplifier output is
connected to the control logic that determines the state
of the fault latch. To avoid tripping the breaker due to
load capacitance during initial power up a higher
threshold is used. The amplifier will detect if the drop
across the sense resistor reaches 166mV and discharge
the gate of the MOSFET if detected. Once the load
voltage approaches the input potential the threshold is
lowered to 70mV. This allows for capacitive load
charging and continuous current sensing without the use
of a fixed sense blanking timer where excessive currents
may develop glitching the input bus prior to breaking.
VC Voltage Regulator and MOSFET Drive:
The biasing scheme in the PI2061 uniquely enables the
gate control relative to SGND and PGND pins via the
resistor R_PG shown in Figure 1. The VC input provides
power to the control circuitry, the charge pump and the
gate driver. An internal regulator clamps the VC voltage
to 11.7V with respect to SGND.
The VC pin is connected through an external resistor to
the input power source and drain of the MOSFET. VC
switches over to the load potential once the gate drive is
enabled and over current condition is not present.
The internal regulator circuit has a comparator to
monitor VC voltage and pulls the gate low when VC to
SGND is lower than the VC Under-Voltage Threshold. As
shown in Figure 1 the lower bias resistor, R_PG is placed
between the SGND connection and the system ground.
Gate Driver:
The PI2061 has an integrated charge pump that
approximately doubles the regulated VC with respect to
SGND enhancing the N-Channel MOSFET gate to source
voltage.
The internal gate driver controls the N-channel MOSFET
such that in the on state, the gate driver applies current
to the MOSFET gate driving it to bring the load up to the
input voltage and into the R_DS(on) condition.
When an over current condition is sensed the gate driver
pulls the gate low to PGND and discharges the MOSFET
gate with 4A peak capability. A Schottky diode (D1 in
Figure 1) from PGND to the MOSFET source is required to
direct the Gate high discharge current into the Source.
The PI2061 applies high gate discharge current for fast
MOSFET turn off when a fault condition occurs to
prevent system disruption. Fast MOSFET turn off may
produce high voltage ringing due to parasitic inductance.
To prevent negative peaks at SN from injecting substrate
current, Schottky diode D2 (from SGND/PGND to SN pin
as shown in Figure 1) is required.
Enable Input: (EN)
This input provides control of the switch state enabling
and disabling with low current level signals. The active
high feature allows pulling/sinking a low current from
this input to disable the breaker. System control can
disable the switch and reset the over current latch by
pulling this pin to a logic low state.
Once enabled, the Gate pin will charge the MOSFET gate
to turn the load on. The load voltage will rise, reach the
input voltage and the device will sense the current
continuously once the POR interval has cleared relative
to the VC to SGND potential. The disable control with this
input is very fast, turning the switch off in typically
200ns. The response to open during an over current
event is typically 120ns and the switch will latch off until
reset by bringing this input low or recycling of the input
power.
Fault Status: (FT)
This open collector pin transitions to high resistance after
the Fault Status is delayed for 5μs when an over-current
fault or disable signal occurs. When the controller input
voltage is in under voltage, (VC - SGND < 7V) this pin is
high resistance as well. When the part is in a normal
operating condition and gate driver is enabled this pin is
low resistance. In high voltage applications this output
must be translated to the system return with external
circuitry. Leave this pin open if unused.
Picor Corporation • picorpower.com
PI2061
Rev 1.4
Page 5 of 16