PRM48BY480X500A00 Datasheet, PDF (39/44 Pages) Vicor Corporation – High Efficiency Converter

DESIGN GUIDELINES (General Operation)
The following guidelines are general guidelines that apply to any
mode of operation.
FPA System Considerations
There are a few system level design considerations that should be
carefully considered when using a PRM and VTM to implement a
Factorized Power Architecture (FPA) system
The VC pin of the PRM should be directly connected to the VC
pin of the VTM. The PRM and VTM coordinate the so start sequence
of the FPA system through this connection. If the VC pins are not
connected the VTM will not start up. When the PRM is ready to start
up, it applies a voltage on VC, which enables and powers the VTM’s
powertrain. The PRM then proceeds to ramp up its output voltage.
Aer approximately 10 ms, VC returns to 0 V and the VTM can then
derive power directly from the factorized bus provided that the
factorized bus voltage is above the minimum specified VTM
operating input voltage when the VC pulse expires.
All VTM faults latch the VTM powertrain off. Input power to the
system as a whole must be recycled or the PRM should be disabled
and enabled by way of its ENABLE pin in order to restart the system.
It is recommended that the voltage on the factorized bus return to
zero before the PRM is re-enabled. Otherwise the so start of the
system may be compromised.
A RL filter should be placed between the PRM and VTM to locally
isolate switching ripple currents that can interfere with module
operation. It is important that the inductance have an impedance
that is much greater than that of the PRM output capacitance and
VTM input capacitance at the switching frequencies of the devices. A
resistor should be placed in shunt to this inductor to dampen the
resultant LC tank. For most cases 100 nH in parallel with 1 Ω is
sufficient to isolate the switching ripple currents.
Verifying Stability
A load step transient response can be used in order to estimate
stability.
Figure 38 illustrates an example of a load step response. Equation
(11) can be used to predict the phase margin based on the ratio of
the “kick” to “droop” (as defined in Fig. 38).
k
Vout
d
Iout
time
time
(a) without adaptive loop
k
Vout
d
Iout
time
time
(b) with adaptive loop
Figure 40 — Load step response example and “droop” vs. “kick”
(a) without Adaptive Loop; (b) with Adaptive Loop.
PRM^TM Regulator
Page 39 of 44
Rev 1.4
11/2015
PRM48By480x500A00
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(11)
Burst Mode Operation
At light loads, the PRM will operate in a burst mode due to minimum
timing constraints. An example burst operation waveform is
illustrated in Figure 39.
For very light loads, and also for higher input voltages, the minimum
time power switching cycle from the powertrain will exceed the
power required by the load. In this case the error amplifier will
periodically drive SHARE/CONROL NODE below the switching
threshold in order to maintain regulation. Switching will cease
momentarily until the error amplifier once again drives
SHARE/CONTROL NODE voltage above the threshold.
Figure 41 — Light load burst mode of operation
Note that during the bursts of switching, the powertrain frequency is
constant, but the number of pulses as well as the time between
bursts is variable. The variability depends on many factors including
input voltage, output voltages, load impedance, and error amplifier
output impedance.
In burst mode, the gain of the SHARE/CONTROL NODE input to the
plant which is modeled in the previous sections is time varying.
Therefore the small signal analysis cannot be directly applied to
burst mode operation.
Input and Output filter design
Figures 14 and 15 provide the total input and output charge per
cycle, as well as switching frequency, of the PRM at full load under
various input and output voltages conditions.
Figure 13 provides the effective internal capacitance of the module.
A conservative estimate of input and output peak-peak voltage
ripple at nominal line and trim is provided by equation (12):
6V

Q_{TO T}
<
I_FL u 0.4
f _SW
C_INT C_EXT
(12)
Q_TOT is the total input (Fig. 14) or output (Fig. 15) charge per
switching cycle at full load, while C_INT is the module internal
effective capacitance at the considered voltage (Fig. 13) and C_EXT is
the external effective capacitance at the considered voltage.
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