PI33XX Datasheet, PDF (34/42 Pages) Vicor Corporation – 8V to 36Vin Cool-Power ZVS B uck Regulator Family

EAO falls below a PSM threshold. Depending on
conditions and component values, this may result in
single pulses or several consecutive pulses followed
by skipped pulses. Skipping cycles significantly
reduces gate drive power and improves light load
efficiency. The regulator will leave PSM once the EAO
rises above the Skip Mode threshold.
Variable Frequency Operation
Each PI33XX is preprogrammed to a base operating
frequency, with respect to the power stage inductor
(see Table 5), to operate at peak efficiency across line
and load variations. At low line and high load
applications, the base frequency will decrease to
accommodate these extreme operating ranges. By
stretching the frequency, the ZVS operation is
preserved throughout the total input line voltage
range therefore maintaining optimum efficiency.
Parallel Operation
Paralleling multiple PI33XX modules can be used to
increase the output current capability of a single
power rail and reduce output voltage ripple.
Vin
Cin
R1
SYNCO
SYNCI
EN
EAO
TRK
L1
Vin
VS1
Vout
PGND
PI33XX
PGD
REM
SYNCI
SYNCO
EN
EAO
TRK
SGND
Vin
Cin
SYNCO
SYNCI
EN
EAO
TRK
L1
Vin
VS1
Vout
PGND
PI33XX
PGD
REM
SYNCI
SYNCO
EN
EAO
TRK
SGND
Cout
Cout
Vout
Figure 3 - PI33XX parallel operation
By connecting the EAO pins and SGND pins of each
module together the units will share the current
equally. When the TRK pins of each unit are
connected together, the units will track each other
during soft-start and all unit EN pins have to be
released to allow the units to start (See Figure 3).
Also, any fault event in any regulator will disable the
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other regulators. The two regulators will be out of
phase with each other reducing output ripple (refer
to Switching Frequency Synchronization).
To provide synchronization between regulators over
the entire operational frequency range, the Parallel
Good (PGD) pin must be connected to the lead
regulator’s SYNCI pin and a 2.5kΩ Resistor, R1, must
be placed between SYNCO return and the lead
regulator’s SYNCI pin, as shown in Figure 3. In this
configuration, at system soft-start, the PGD pin pulls
SYNCI low forcing the lead regulator to initialize the
open-loop startup synchronization. Once the
regulators reach regulation, SYNCI is released and the
system is now synchronized in a closed-loop
configuration which allows the system to adjust, on
the fly, when any of the individual regulators begin to
enter variable frequency mode in the loop.
Multi-phasing three regulators is possible (PI33XX-20
and PI33XX-21 only) with no change to the basic
single-phase design. For more information about
how to program phase delays within the regulator,
please refer to Picor application note PI33XX-2X
Multi-Phase Design Guide.
I²C Interface Operation
PI33XX-20 and PI33XX-21 provide an I²C digital
interface that enables the user to program the EN pin
polarity (from high to low assertion) and switching
frequency synchronization phase/delay. These are
one time programmable options to the device.
Also, the PI33XX-20 and PI33XX-21 allow for dynamic
Vout margining via I²C that is useful during
development (settings stored in volatile memory only
and not retained by the device). The PI33XX-20 and
PI33XX-21 also have the option for fault telemetry
including:
 Over temperature protection
 Fast/Slow current limit
 Output voltage high
 Input overvoltage
 Input undervoltage
Rev 1.4
11/2012
Cool-Power^®
Page 34 of 42