PI3302-00-LGIZ Datasheet, PDF (32/42 Pages) Vicor Corporation – 8 V to 36 Vin Cool-Power ZVS Buck Regulator Family

PI33xx-x0
Functional Description
The PI33xx-x0 is a family of highly integrated ZVS-Buck regulators.
The PI33xx-x0 has a set output voltage that is trimmable within
a prescribed range shown in Table 1. Performance and maximum
output current are characterized with a specific external power
inductor (see Table 4).
L1
V_IN
V_IN
VS1
C_IN
PI33xx
PGND
V_OUT
REM
SYNCI
SYNCO
EN
TRK
ADJ
EAO
V_OUT
C_OUT
Figure 58 — ZVS-Buck with required components
For basic operation, Figure 58 shows the connections and compo-
nents required. No additional design or settings
are required.
ENABLE (EN)
EN is the enable pin of the converter. The EN Pin is referenced to
SGND and permits the user to turn the regulator on or off. The
EN default polarity is a positive logic assertion. If the EN pin is left
floating or asserted high, the converter output is enabled. Pulling
EN pin below 0.8 Vdc with respect to SGND will disable the regu-
lator output.
The EN input polarity can be programmed (PI33xx-20 device
versions only) via the I²C data bus. When the EN pin polarity is
programmed for negative logic assertion; and if the EN pin is left
floating, the regulator output is enabled. Pulling the EN pin above
1.0 Vdc with respect to SGND, will disable the regulator output.
Remote Sensing
An internal 100 Ω resistor is connected between REM pin and
V_OUT pin to provide regulation when the REM connection is
broken. Referring to Figure 58, it is important to note that L1 and
C_OUT are the output filter and the local sense point for the power
supply output. As such, the REM pin should be connected at C_OUT
as the default local sense connection unless remote sensing to
compensate additional distribution losses in the system. The REM
pin should not be left floating.
Switching Frequency Synchronization
The SYNCI input allows the user to synchronize the controller
switching frequency by an external clock referenced to SGND.
The external clock can synchronize the unit between 50% and
110% of the preset switching frequency (fS). For PI33xx-20
device versions only, the phase delay can be programmed via I²C
bus with respect to the clock applied at SYNCI pin. Phase delay
allows PI33xx-20 regulators to be paralleled and operate in an
interleaving mode.
The PI33xx-x0 default for SYNCI is to sync with respect to the
falling edge of the applied clock providing 180° phase shift from
SYNCO. This allows for the paralleling of two PI33xx-x0 devices
without the need for further user programming or external sync
clock circuitry. The user can change the SYNCI polarity to sync
with the external clock rising edge via the I²C data bus (PI33xx-20
device versions only).
When using the internal oscillator, the SYNCO pin provides a
5 V clock that can be used to sync other regulators. Therefore,
one PI33xx-x0 can act as the lead regulator and have additional
PI33xx-x0s running in parallel and interleaved.
Soft-Start
The PI33xx-x0 includes an internal soft-start capacitor to ramp the
output voltage in 2 ms from 0 V to full output voltage. Connect-
ing an external capacitor from the TRK pin to SGND will increase
the start-up ramp period. See, “Soft Start Adjustment and Track,”
in the Applications Description section for more details.
Output Voltage Trim
The PI33xx-x0 output voltage can be trimmed up from the preset
output by connecting a resistor from ADJ pin to SGND and can be
trimmed down by connecting a resistor from ADJ pin to V_OUT. The
Table 1 defines the voltage ranges for the PI33xx-x0 family.
Device
PI3311-x0-LGIZ
PI3318-x0-LGIZ
PI3312-x0-LGIZ
PI3301-x0-LGIZ
PI3302-x0-LGIZ
PI3303-x0-LGIZ
PI3305-x0-LGIZ
Output Voltage
Set
Range
1.0 V
1.0 to 1.4 V
1.8 V
1.4 to 2.0 V
2.5 V
2.0 to 3.1 V
3.3 V
2.3 to 4.1 V
5.0 V
3.3 to 6.5 V
12 V
6.5 to 13.0 V
15 V
10.0 to 16.0 V
Table 1 — PI33xx-x0 family output voltage range
Cool-Power®
Page 32 of 42
Rev 2.0
02/2016
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