PI3749-X0 Datasheet, PDF (20/26 Pages) Vicor Corporation – 16V to 34VIN, 12V to 28VOUT, 240W Cool-Power ZVS Buck-Boost

PI3749-x0
I²C Addressing
The PI3749-20 is hardware compatible with the NXP I²C Bus Specification Version 2.1, January 2000, in Standard Mode (100kHz) for all bus
timing and voltage levels up to 5.5V. It operates as a slave on the I²C bus.
The PI3749-20 I²C interface responds to the address programmed by the two I²C Address pins, ADR1 and ADR0. The address pins are
three level inputs, providing nine possible combination pairs, although only eight of these combinations are unique, as shown in table 3.
Considering only the 7 bit address sub-field, the high-order address bits <6> through <4> are hardcoded to 4’b1001, while the lower order
address bits <3> through <0> are modified by the ADRx pins.
ADDRx state
ADR1 ADR0
Resultant I²C address sub-field
Sub-field bit positions <7.1>
Hexadecimal Decimal
Binary
Fully formed address write word
(including lsb of the transfer set for a write)
Binary
L
L
7’h48
72
7’b100_1000 8’b1001_0001
L
M
7’h49
73
7’b100_1001 8’b1001_0011
L
H
7’h4A
74
7’b100_1010 8’b1001_0101
M
L
7’h4B
75
7’b100_1011 8’b1001_0111
M
M
7’h4C
76
7’b100_1100 8’b1001_1001
M
H
7’h4D
77
7’b100_1101 8’b1001_1011
H
L
7’h4E
78
7’b100_1110 8’b1001_1101
H
M
7’h4F
79
7’b100_1111 8’b1001_1111
H
H
7’h4F
79
7’b100_1111 8’b1001_1111
Table 3 — I²C Address selection
Note that the state of the ADRx pins is resolved on each I2C address transfer. Therefore the PI3749-20 address can be changed while the
regulator is powered up and in operation.
I²C Command Structure
Depending on the state of the read/write bit, two types of transfers are possible:
a. Write: Data transferred from the I2C master to the PI3749-20 slave
The first byte is transmitted by the master and includes the slave address and the R/W bit set to write (as shown in the last column of table 3.)
The second byte is also transmitted by the master and is the write data.
The slave responds between each byte with an acknowledge bit.
b. Read: Data returned from the PI3749-20 slave to the master
The first byte is transmitted by the master and includes the slave address but the R/W bit is set to read. The slave responds to the first
byte (the address transmitted by the master) with an acknowledge bit.
The second byte is transmitted by the slave back to the master and is the read data. The master responds after the read data byte
with a not-acknowledge bit (since the PI3749-20 read data are all single byte registers).
Figure 28 — Data transfer on the I²C bus
Per the I²C standard, the master generates all serial clock pulses, and all data is transferred MSB first.
Cool-Power^® ZVS Switching Regulators
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Rev 1.6
09/2016
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