PI3749-X0 Datasheet, PDF (18/26 Pages) Vicor Corporation – 16V to 34VIN, 12V to 28VOUT, 240W Cool-Power ZVS Buck-Boost

number of ceramic capacitors used to calculate the individual
capacitor’s RMS current. Table 2 includes the recommended
input and output ceramic capacitor. It is very important to verify
that the voltage supply source as well as the interconnecting line
are stable and do not oscillate.
Input Filter case 1; Inductive source and local, external, input
decoupling capacitance with negligible ESR (i.e.: ceramic type)
The voltage source impedance can be modeled as a series Rline
Lline circuit. The high performance ceramic decoupling capacitors
will not significantly damp the network because of their low ESR;
therefore in order to guarantee stability the following conditions
must be verified:
( ) ^{Rline >}
L_line
C + C _{IN_INT}
IN_EXT
• r_{EQ_IN}
(3)
R_line << r_{EQ_IN}
(4)
Where, r_{EQ_IN} can be calculated by dividing the lowest line
voltage by the full load input current. It is critical that the
line source impedance be at least an octave lower than the
converter’s dynamic input resistance, Equation (4). However,
Rline cannot be made arbitrarily low otherwise Equation (3)
is violated and the system will show instability, due to under-
damped RLC input network.
Input Filter case 2; Inductive source and local, external input
decoupling capacitance with significant R_{CIN_EXT} ESR
(i.e.: electrolytic type)
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor L_line. Notice
that, the high performance ceramic capacitors C_{IN_INT} within
the PI3749-x0 should be included in the external electrolytic
capacitance value for this purpose. The stability criteria will be:
r > R _{EQ_IN}
CIN_EXT
(5)
L_line
C • R _{IN_INT}
CIN_EXT
< r_{EQ_IN}
(6)
Equation (6) shows that if the aggregate ESR is too small – for
example by using very high quality input capacitors (C_{IN_EXT})
– the system will be under-damped and may even become
destabilized. Again, an octave of design margin in satisfying
Equation (5) should be considered the minimum.
Note: When applying an electrolytic capacitor for input filter
damping the ESR value must be chosen to avoid loss of converter
efficiency and excessive power dissipation in the
electrolytic capacitor.
PI3749-x0
Parallel Operation
PI3749-x0 can be connected in parallel up to two phases, with
interleaving. Parallel interleaved modules can be used to increase
the output current capability of a single power rail and reduce
output voltage ripple. Figure 27 shows the proper connection
of two regulators in parallel interleaved operation. Connecting
a higher number of modules (up to six maximum) is possible
without interleaving or synchronization. Connecting groups
of interleaved modules would be the best configuration for
applications requiring higher current than two modules can
produce. The user must consider a worst case sharing error of
+/-10% when considering a two unit parallel system to avoid
overloading one module or tripping current limit during
load transients.
L1
VS1 VS2
Vin
Vin
Vout
Cin
PGND
C out
PI3749-x0
R1
SYNCO (#2)
PGD
SYNCI
(#1)
EAIN
SYNCI (#2)
SYNCO
EN (#2)
EN
EAO (#2)
EAO
TRK (#2)
TRK
SGND
L2
Vin
Vin ^VS1
VS2
Vout
Cin
PGND
C out
PI3749-x0
SYNCO (#1)
PGD
SYNCI
(#2)
EAIN
SYNCI (#1)
SYNCO
EN (#1)
EN
EAO (#1)
TRK (#1)
EAO
TRK
SGND
Vout
Figure 27 — PI3749-x0 parallel operation
By connecting the EAO pins and SGND pins of each module
together, the regulators will share the output current equally,
provided each power inductor is the same value and the output
ripple is not excessive. Connecting all TRK pins will force all units
to track each other during soft-start. Additionally, all units EN
pins must be released to allow the units to start (See Figure 27).
To provide synchronization between regulators over the entire
operational frequency range, the Power Good (PGD) pin must
be connected to the lead regulator’s (#1) SYNCI pin and a 2.5kΩ
Resistor, R1, must be placed between SYNCO (#2) return and
the lead regulator’s SYNCI (#1) pin, as shown in Figure 27. In
this configuration, at system soft-start, the PGD pin pulls SYNCI
low forcing the lead regulator to initialize the open-loop startup
synchronization. Once the regulators reach regulation, SYNCI
is released and the system is now synchronized in a closed-
loop configuration which allows the system to maintain correct
synchronization when any of the individual regulators begin to
enter variable frequency mode.
Any fault event flagged by one regulator will disable the other
regulators. The regulators will not be synchronized during a fault
or during startup (resulting in higher output ripple for that period
of time) until the PGD pin is released.
Cool-Power^® ZVS Switching Regulators
Page 18 of 26
Rev 1.6
09/2016
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