PI2002 Datasheet, PDF (14/23 Pages) Vicor Corporation – Active ORing Controller IC with Load Disconnect Feature

Application Information:
The PI2002 is designed to replace ORing diodes and
load disconnect switches in high current redundant
power architectures. Replacing a traditional diode
with a PI2002 controller IC and two low on-state
resistance back-to-back N-channel MOSFETs will
result in significant power dissipation reduction as well
as board space reduction, efficiency improvement,
input power source and output load protection and
additional protection features. This section describes
in detail the procedure to follow when designing with
the PI2002 Active ORing controller and two back-to-
back N-Channel MOSFETs. Two design examples
are presented, one Active ORing with load disconnect
design example and one low side disconnect switch
example.
Fault Indication:
FT output pin is an open collector and should be
pulled up to the logic voltage or to the controller VC
via a resistor (10KΩ)
Over-Current Timer: OCT
Connect a capacitor, equal or less than 20nF, to set
off time after over-current shutdown (see Figure 3).
Short Circuit Detect: SCD
Connect SCD pin to VC to avoid inrush current into a
high capacitive load, or connect SCD to GND pin for
fast MOSFET turn on.
Note: The SCD pin is not available in the SO-8
package and the controller is set for low Gate
source current, 300µA.
Auxiliary Power Supply (Vaux):
Vaux is an independent power source required to
supply power to the PI2002 VC input. The Vaux
voltage should be higher than Vin (redundant power
source output voltage) by the required gate-to-source
voltage (Vgs) to fully enhance the MOSFET, plus 0.5V
maximum gate to VC headroom (VHD_VC-G)
Vaux = Vin + Vgs + VHD_VC-G
Where, VHD_VC-G is defined as the 0.5V maximum drop
from VC in the Gate Voltage High (V_G) specification in
the Gate Driver section of the Electrical Specification.
For example, if the bus voltage is 3.3V and the
MOSFET requires 4.5V of Vgs to fully enhance the
MOSFET, then Vaux should be at least 3.3V + 4.5V +
0.5V = 8.3V.
If Vaux is higher than 15V then a bias resistor (Rbias)
is required, and should be connected between the
PI2002 VC pin and Vaux. The resistor is selected
based on the input voltage range.
Minimize the resistor value for low Vaux voltage levels
to avoid a voltage drop that may reduce the VC
voltage lower than required to drive the gate of the
MOSFET. Select the value of Rbias using the
following equations:
Rbias = ^{Vauxmin − VCclamp}
IC _max
Rbias maximum power dissipation:
Pd _Rbias
=
(Vaux_max −VC_clamp ) ²
Rbias
Rbias maximum power dissipation is at maximum
input voltage and minimum clamp voltage (15V).
Where:
Vaux_min : Vaux minimum voltage
Vaux_max : Vaux maximum voltage
VC_Clamp : Controller clamp voltage, 15.5V
IC_max : Controller maximum bias current (4.2mA)
N-Channel MOSFET Selection:
There are several factors that affect the MOSFET
selection including cost, on-state resistance (Rds(on)),
current rating, power dissipation, thermal conductivity,
drain-to-source breakdown voltage (BVdss), gate-to-
source voltage rating (Vgs), and gate threshold
voltage (Vgs_(TH)).
The first step is to select suitable MOSFETs based on
the BVdss requirement for the application. The BVdss
voltage rating should be higher than the applied Vin
voltage plus expected transient voltages. Stray
parasitic inductance in the circuit can also contribute
to significant transient voltage conditions, particularly
during MOSFET turn-off after a reverse current fault
has been detected. In Active ORing applications when
one of the input power sources is shorted, a large
reverse current is sourced from the circuit output
through the MOSFET. Depending on the output
impedance of the system, the reverse current may
reach over 60A in some conditions before the
MOSFET is turned off. Such high current conditions
will store energy even in a small parasitic element.
For example, a 1nH parasitic inductance with 60A
reverse current will store 1.8µJ (½Li²). When the
MOSFET is turned off, the stored energy will be
released and will produce high negative voltage
ringing at the MOSFETs input. This event will create a
high voltage difference across the MOSFETs.
Note:
Since the two MOSFETs are connected in to back-to-
back configuration, the maximum breaking voltage is
BVdss of one MOSFET plus one diode forward
voltage.
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 14 of 23