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BCM3814B60E10A5C02 Datasheet, PDF (11/38 Pages) Vicor Corporation – Isolated, Fixed-Ratio DC-DC Converter
BCM3814x60E10A5yzz
Serial Clock input (SCL) AND Serial Data (SDA) Pins
• High‐power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is signal not supported.
• PMBusTM command compatible.
• The internal µC requires the use of a flip‐flop to drive SSTOP. See system diagram section for more details.
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
Electrical Parameters
Input Voltage Threshold
DIGITAL
INPUT/OUTPUT
Output Voltage Threshold
Regular
Operation
Leakage current
Signal Sink Current
Signal Capacitive Load
Signal Noise Immunity
Timing Parameters
Operating Frequency
Free time between
Stop and Start Condition
Hold time after Start or
Repeated Start condition
Repeat Start Condition
Setup time
Stop Condition setup time
Data Hold time
Data Setup time
Clock low time out
Clock low period
Clock high period
Cumulative clock low
extend time
Clock or Data Fall time
VIH
VVDD_IN = 3.3V
2.1
VIL
VVDD_IN = 3.3V
VOH
VVDD_IN = 3.3V
3
VOL
VVDD_IN = 3.3V
ILEAK‐PIN Unpowered device
ILOAD
VOL = 0.4V
4
CI
Total capacitive load of
one device pin
VNOISE_PP 10MHz to 100MHz
300
FSMB
Idle state = 0Hz
10
tBUF
1.3
tHD:STA
First clock is generated
after this hold time
0.6
tSU:STA
0.6
tSU:STO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
tHIGH
0.6
300
100
25
1.3
0.6
tLOW:SEXT
tF
Measured from
(VIL_MAX ‐ 0.15) to (VIH_MIN + 0.15)
20
Clock or Data Rise time
tR
0.9 • VVDD_IN_MAX to (VIL_MAX ‐ 0.15)
20
TYP MAX UNIT
V
0.8 V
V
0.4 V
10 µA
mA
10 pF
mV
400 KHz
µs
µs
µs
µs
ns
ns
35 ms
µs
50 µs
25 ms
300 ns
300 ns
SCL
VIH
VIL
tLOW tR
SDA
VIH
VIL
tBUF
P
S
tHD,STA
tHD,DAT
tF
tHIGH
tSU,DAT
tSU,STA
S
tSU,STO
P
BCM® in a VIA Package
Page 11 of 38
Rev 1.1
05/2016
vicorpower.com
800 927.9474