FX-427_08 Datasheet, PDF (5/8 Pages) Vectron International, Inc – Low Jitter Frequency Translator

Pin Configuration
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
SEL0
SEL1
GND
I/O
I
I
GND
VMON O
OD
I
LD
O
FOUT1
CFOUT1
FOUT2
CFOUT2
GND
O
O
O
O
GND
Figure 6. Pin Configuration
Table 7. Pin Functions
Level
LVCMOS
Frequency Select - see table 3
Function
LVCOMS
Supply
LVCMOS
LVCMOS
LCPECL
LVPECL
Frequency Select – see table 3
Case and Electrical Ground
Not present
VCXO Control Voltage Monitor
Under locked conditions VMON should be > 0.3V and <3.0V. The input fre-
quency may be out of range if the voltage exceeds these levels
Output Disable
Disabled = Logic “1”
Enabled = Logic “0” or no connect
Lock Detect
Locked = Logic “1”
Loss of Lock = Logic “0”
Frequency Output – Primary
Complimentary Frequency Output - Primary
LVPECL
Divided-Down VCSO/VCXO Output, or Disabled
LVPECL
Supply
Complimentary Divided-Down VCSO/VCXO Output, or Disabled
Case and Electrical Ground
13
FIN
I
LVCMOS or
LVPECL
Input Frequency – AC Coupled
14
VCC
VCC
Supply
Power Supply Voltage (3.3 V ±5%)
LVCMOS input signal levels are valid for input frequencies < 100 MHz.
SEL 0
0
0
1
1
SEL 1
0
1
0
1
Table 8. Control Logic (LVCMOS)
CLock Input
FIN
1
FIN
2
FIN
3
FIN
4
Page 5 of 8
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com