VC-708_11 Datasheet, PDF (4/7 Pages) Vectron International, Inc – LVPECL, LVDS Crystal Oscillator Data Sheet Ultra Low Phase Noise

Table 3. Pinout
Pin #
Symbol
1
NC
2
NC
3
GND
4
f
O
5
Cf
O
6
V
DD
1.78
Package and Pinout
Function
No Internal Connection is made
No Internal Connection is made
Electrical and Lid Ground
Output Frequency
Complementary Output Frequency
Supply Voltage
7.0±0.15
6
5
4
VC-708
Frequency
Date Code
5.0±0.15
1
2
3
1.96
1.40
1.20
1
2
3
3.66
Bottom View
3.57
6
5
4
1.8 max
2.54
5.08
Figure 2. Pad Layout
Units are mm
2.54
5.08
Figure 3. Package Outline Drawing
LVPECL Application Diagrams
V_DD
1
6
NC
2
5
NC
3
4
140 ȍ
0.01uF
0.01uF
0.01uF
140 ȍ
Figure 4. Single Resistor Termination Scheme
Resistor values are typically 140 ohms for 3.3V operation and
84 ohms for 2.5V operation.
Figure 5. Pull-Up Pull Down Termination
Resistor values shown are typical for 3.3 V opertaion.
For 2.5V operation, the resistor to ground is 62 ohms and
the resistor to supply is 250 ohms
The VC-708 incorporates a standard PECL output scheme, which are unterminated FET drains. There are numerous application notes on terminating and
interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, and a pull-up/pull-down scheme as shown in Figure 5.
AC coupling capacitor are optional, depending on the application and the input logic requirements of the next stage.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left untermi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
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