FX-700_09 Datasheet, PDF (4/7 Pages) Vectron International, Inc – Low Jitter Frequency Translator

Outline Drawing
Dimensions in mm.
Suggested Pad Layout
Figure 5. Outline Diagram
Pad #
1
2
3
4
Symbol
V
DD
V
DA
V_COUT
Tri-state¹
Table 7. Pin Functions
Function
Digital PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
Analog PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
Control Voltage
Logic Low = Output Disable / Logic High = Output Enabled
5
C1
Passive Loop Filter Node
6
FIN
Input Frequency
7
GND
Cover and Electrical Ground
8
LD²
Lock Detect
9
GNDB
Output Buffer Ground
10
FOUT
Output Frequency
11
VDB
Output Buffer Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
12
VCXO
VCXO Input
IN
13
VCXO
VCXO Output
OUT
14
V
VCXO Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
DO
15
N.C.
No Internal Connection Made
16
V
VCXO Control Voltage Input
CIN
1 Tri-state must be driven to a logic high or a logic low, there is no internal pull up or pull down resistor (tie pin to VDD for PLL operation).
2 LD is an open collector output requiring a 30k ohm minimum pull-up resistor to VDD. LD output is logic high under locked
condition, logic low for no input at FIN, and for “out-of-lock” condition LD transitions between logic low and
high at the phase detector frequency.
Page 4 of 7
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 31Mar2009