FX-424 Datasheet, PDF (3/8 Pages) Vectron International, Inc – Low Jitter Frequency Translator

FX-424 Low Jitter Frequency Translator
Figure 4. Pin Configuration
Table 2. Pin Out
Pin # Symbol I/O
Level
Function
1
SEL0
I
LVTTL
Input Frequency Select*
2
SEL1
I
LVTTL
Input Frequency Select*
3
GND
GND
Supply
Case and Electrical Ground
4
Not present
5
VMON
O
Analog
VCXO Control Voltage Monitor
Under locked conditions VMON should be > 0.3V and <3.0V. The input
frequency may be out of range if the voltage exceeds these levels.
6
OD
I
LVCMOS
Output Disable
Disabled = Logic “1”
Enabled = Logic “0” or no connect
7
GND
GND
Supply
Case and Electrical Ground
8
FOUT
O
LVPECL or
LVCMOS
Frequency Output
9
CFOUT
O or
GND
LVPECL or
LVCMOS
Complementary Frequency Output – Note for LVCMOS option this pad
will be tied to GND.
10
LD
O
LVCMOS
Lock Detect
Locked = Logic “1”
Loss of Signal = Logic “0”
11
GND
GND
Supply
Case and Electrical Ground
12
GND
GND
Supply
Case and Electrical Ground
13
FIN
I
LVCMOS or _{Input Frequency. The FX-424 series AC couples the input for handling of}
LVPECL
either LVCMOS or LVPECL input signals.
14
VCC
VCC
Supply
Power Supply Voltage (3.3 V ±5%)
* For applications requiring two to four input frequencies, Vectron will assign a unique part number and the Input Frequency versus SEL[1:0]
settings will be provided in a Specification Control Drawing. For single input configurations it is recommended that SEL0 and SEL1 are tied
to ground.
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 3 of 8
Tel: 1-88-VECTRON-1 • Web: www.vectron.com
Rev: 12Dec05