J-TYPE Datasheet, PDF (2/8 Pages) Vectron International, Inc – Voltage Controlled Crystal Oscillator

J-Type Voltage Controlled Crystal Oscillator
CMOS Output Option
Electrical Performance @ 25°C for the CMOS output option
Parameter
Supply Voltage¹, +5 volt option
+3.3 volt option
Supply Current
Center Frequency, see ordering information
Operating Temperature, see ordering info
Absolute Pull Range over the operating tempera-
ture range, aging and power supply Vc=0.5 to
4.5 at 5V supply or 0.3 to 3.0 V at 3.3V supply
see ordering information for options
Gain Transfer
(Frequency vs. Control Voltage)
Output Level High²
Output Level Low²
Output Rise/Fall Time²
Duty Cycle³, see ordering info
Control Input Leakage
Control Voltage Modulation Bandwidth
RMS Jitter, Output=12.0-77.760 MHz
RMS Jitter, Output=12.0-77.760 MHz.
Band=12.0 KHz - 20 MHz
Control Range
Maximum Supply Voltage
Storage Temperature
Soldering Temp./Time
Symbol
FN
TOP
APR
KV
VOH
VOL
tR/ tF
SYM
IL
BW
TS
TLS
Minimum Typical Maximum
4.5
5.0
5.5
3.0
3.3
3.6
10mA + 0.25mA per MHz, typical
1.024
77.760
0/70, -40/85
±50 to ±100
Unit
Vdc
Vdc
MHz
°C
ppm
Positive
0.8*Vcc
-
V
-
0.1*Vcc
V
5
ns
45/55 or 40/60
%
1
uA
-
10
-
kHz
3
ps
<0.5
ps
0
VDD
7
V
-55
-
125
°C
-
-
220/10
°C/s
1. Power supply bypass is required and a 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended.
2. Figure 1 defines these parameters. Figure 2 illustrates the load used to test devices.
3. Duty cycle is defined as on-time versus period at 1.4 V for TTL, and 2.5 V for CMOS (5volt supply) and at 1.65 V for CMOS (3.3 volt operation)
Pin Out Information for the CMOS output option
Pin Symbol
1
Vc
2
Tri-State¹
3
GND
4
Output
5
CMOS/TTL
select^1,2
6
VCC
Function
VCXO Control Voltage.
TTL logic low disables output
TTL logic high, or no connect, enables output
Case and electrical ground.
VCXO Output
TTL logic low optimizes symmetry for CMOS
TTL logic high, or NC, optimizes symmetry for TTL.
Power Supply Voltage (5.0 V or 3.3V ±10%)
1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2.
2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin for fre-
quencies < 12MHz.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Fax: 1-888-FAX-VECTRON
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