CD-700_09 Datasheet, PDF (2/12 Pages) Vectron International, Inc – Complete VCXO Based Phase Lock Loop

Performance Specifications
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical
Output Frequency (ordering option)
OUT 1, 5.0 V option
OUT 1, 3.3 V option
1.000
1.000
Supply Voltage¹
+5.0
+3.3
V
4.5
5.0
DD
2.97
3.3
Supply Current
Output Logic Levels
Output Logic High²
Output Logic Low²
Output Transition Times
Rise Time²
Fall Time²
Input Logic Levels
Input Logic High²
Input Logic Low²
Loss of Signal Indication
Output Logic High²
Output Logic Low²
Nominal Frequency on Loss of Signal
Output 1
Output 2
I
DD
V
2.5
OH
V
OL
t_R
t
F
V
2.0
IH
V
IL
V
2.5
OH
V
OL
Symmetry or Duty Cycle³
Out 1
Out 2
RCLK
SYM1
SYM2
RCLK
Absolute Pull Range (ordering option)
APR
over operating temperure, aging, and power
supply variations
±50
±80
±100
Test Conditions for APR (+5.0 V option)
Test Conditions for APR (+3.3 V option)
Gain Transfer
V
0.5
C
V
0.3
C
Kv
Positive
Phase Detector Gain
+5.0 V option
+3.3 V option
Kv
0.53
0.35
Operating temperature (ordering option)
T
OP
Control Voltage Leakage Current
I_VCXO
0/70 or -40/85
Maximum
77.760
77.760
5.5
3.63
63
0.5
3.0
3.0
0.5
0.5
±75
±75
40/60
45/55
40/60
4.5
3.0
±1.0
Units
MHz
MHz
V
V
mA
V
V
ns
ns
V
V
V
V
ppm
ppm
%
%
%
ppm
V
V
rad/V
rad/V
°C
μA
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which these parameters
are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RCLK, RDATA Test Conditions (25 ±50C)
Page 2 of 12
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 30Mar2009