VN16218 Datasheet, PDF (1/11 Pages) Vaishali Semiconductor – 2.5 Gigabit SERDES Transceiver

Advance Information
VN16218
2.5 Gigabit SERDES Transceiver
Applications
•= Fast serial backplane transceiver
•= High-speed point-to-point links
General Description
The VN16218 is a low power single chip, 2.5GBd transceiver. It provides a 2.5GBd serial link interface in
the physical layer and includes a Serialize/Deserialize (SERDES) capability. Other functions include clock
generation, clock data recovery, and word synchronization. In addition, an internal loopback function is
provided for system debugging.
The VN16218 is ideal for 2.5 Gigabit, serial backplane and proprietary point-to-point applications. The
device supports both fiber-optic and copper media.
The transmitter section of the VN16218 accepts 20-bit wide TTL data and latches it on the rising edge of the
incoming Transmit Byte Clock (TBC) and serializes the data onto the TX± differential outputs, at a baud rate
that is twenty times the TBC frequency. The data is converted to a high-speed serial data stream. The
transmit PLL locks to the 125 MHz TBC. This clock is then multiplied by 20 to supply a 2.5 GHz serial clock
for parallel-to-serial conversion. The high-speed serial outputs can interface directly with copper cables or
PCB traces. Where optical transmission is required, the outputs can connect to a separate optical module.
When copper lines are the medium, equalization is available for improved performance.
The receiver section of the VN16218 accepts a serial data stream of 2.5 GBd and recovers 20 bit parallel
data. The receiver PLL locks on to the incoming serial signal and recovers the high-speed incoming clock
and data. The serial data is converted back into 20-bit parallel data format. Byte alignment is accomplished
by optional recognition of the K28.5+ comma character.
The recovered parallel data is sent to CMOS outputs, together with two 125 MHz clocks, RBC and RBCN,
that are 180 degrees out of phase from each other.
Features
•= 20-bit wide parallel Tx, Rx busses
•= 20-bit LVTTL interface for transmit and
receive data at 125 MHz
•= 125 MHz complementary receive and
byte clocks
•= Low Power Consumption
•= ESD rating >2000V (Human Body Model)
or >200V (Machine Model)
•= Parallel loopback mode
•= Available in 14 mm x 14 mm
LQFP package
•= Differential PECL serial output
•= I/O power supply 3.3V
•= Core power supply 1.8 V
2001-11-09
Page 1
MDSN-0003-00
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax [phone]