UM805 Datasheet, PDF (7/14 Pages) Union Semiconductor, Inc. – Voltage Monitors with Manual Reset Input

UM805/811/812
Detailed Description
RESET Timing
The reset signal is asserted LOW for the UM811 and HIGH for the UM812 when the power supply
voltage falls below the threshold trip voltage and remains asserted for at least 140ms after the power
supply voltage has risen above the threshold.
5V
V_CC
0V
V_TH
V_TH
t_RP
5V
RESET
0V
5V
RESET
0V
Figure 1. RESET vs. V_CC Timing Diagram
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The reset signal is asserted LOW for the UM811 and HIGH for the UM812 when M R is low and
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remains asserted for at least 140ms after M R is high.
HIGH
MR
t_MR
LOW
t_MD
t_RP
V_CC
RESET
0V
V_CC
RESET
0V
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Figure 2. RESET vs. MR Timing Diagram
Reset Output
A microprocessor’s (µP’s) reset input starts the µP in a known state. These μP supervisory circuits
assert reset to prevent code execution errors during power-up, power-down, or brownout conditions.
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RESET is guaranteed to be a logic low for V_CC > 1V. Once V_CC exceeds the reset threshold, an
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internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes
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http://www.union-ic.com Rev.01 Jan.2015
7/14