TQP7M9105_15 Datasheet, PDF (8/9 Pages) TriQuint Semiconductor – 1W High Linearity Amplifier

Package Marking and Dimensions
TQP7M9105
1W High Linearity Amplifier
Package Marking
Product Identifier
Lot Code
D
A
D1
7M9105
YXXX
B
e
e1
E
E1
H
L
2X B1
C
7°
D1
HALF ETCHING
DEPTH 0.001"
D1
Alternate Backside Patterns - Reflow Compatible
(Part may be supplied with either pattern)
SYMBOL
A
B
B1
C
D
D1
MIN
1.40
(.055)
.44
(.017)
.36
(.014)
.35
(.014)
4.40
(.173)
1.62
(.064)
TYP
1.50
(.059)
.50
(.020)
.42
(.0165)
.40
(.016)
4.50
(.177)
1.73
(.068)
MAX
1.60
(.063)
.56
(.022)
.48
(.019)
.44
(.017)
4.60
(.181)
1.83
(.072)
SYMBOL
E
E1
e
e1
H
L
MIN
2.29
(.090)
2.13
(.084)
3.94
(.155)
.89
(.035)
TYP
2.50
(.098)
2.20
(.087)
1.50 BSC
(.059)
3.00 BSC
(.118)
4.10
(.161)
1.10
(.043)
MAX
2.60
(.102)
2.29
(.090)
4.25
(.167)
1.20
(.047)
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Dimension and tolerance formats conform to ASME Y14.4M-1994.
3. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP-012.
4. Contact plating: NiPdAu
PCB Mounting Pattern
29X ₃
4.50 [0.177]
3.86 [0.152]
1.26 [0.050]
0.63 [0.025]
0.76 [0.030]
Ø.254 (.010) PLATED THRU VIA HOLES
PACKAGE OUTLINE
2X 0.58 [0.023]
2X 1.27 [0.050]
2.65 [0.104]
0.64 [0.025]
0.86 [0.034]
2X 0.86 [0.034]
3.86 [0.152]
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Use 1 oz. copper minimum for top and bottom layer metal.
3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation.
4. Do not remove or minimize via hole structure in the PCB. Thermal and RF grounding is critical.
5. We recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10”).
6. Ensure good package backside paddle solder attach for reliable operation and best electrical performance.
Datasheet: Rev D 12-16-14
© 2014 TriQuint
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Disclaimer: Subject to change without notice
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