TQ8103 Datasheet, PDF (2/9 Pages) TriQuint Semiconductor – 622 Mb/s Clock & Data Recovery

TQ8103
Figure 2. TQ8103 Block Diagram
SINO
SINI
V_DD
DQ
+16
Loc k
Detect
V_REF
Phase
Detect
V_EE
Mux
Charge
Pump
VCO
CKREF
F requency
Detect
DOUTP
D_OUTN
LOCK
CKOUTP
CKOUTN
Functional Description
The TQ8103 CDR integrates separate detectors for
acquiring frequency lock and maintaining precise phase
lock. When the CDR is locked onto an incoming NRZ
data stream, its phase-detect circuitry compares the
phase of the incoming NRZ data and the phase of the
generated 622.08 MHz clock. When they differ, the
resulting error signal nulls the phase difference and
puts the generated 622.08 MHz clock back in phase
with the incoming data. In this mode, the LOCK output
is high.
The phase-detect circuit operates only when the
incoming NRZ data transitions between states. SONET
and SDH employ scrambling, which provides an
average transition density of 50 percent; however, some
data patterns can generate legitimate scrambled signals
with a significant number of consecutive ones or zeros.
The TQ8103 maintains lock over bit sequences of over
100 consecutive zeros or ones.
When the input data is lost or too many bit times occur
without a transition, the PLL (which generates the
622.08 MHz clock) eventually drifts. The lock-detect
circuit constantly compares the generated 622.08 MHz
clock (divided by 16) and the external 38.88 MHz
reference. When the PLL drifts more than 2000 PPM
from the reference, the LOCK output goes low.
The SEL input selects between the phase-detect and
frequency-detect circuits. When the PLL drifts out of
lock, taking SEL low reverses the drift by switching in
the frequency-detect circuit. Connecting the LOCK
output directly to the SEL input should ensure that
frequency lock is maintained in the absence of data.
It is recommended, however, that a low-pass filter be
added between LOCK and SEL to allow for orderly
transitions between these circuits. Once the PLL
frequency is within 500 PPM of the reference, the LOCK
output returns high. As the SEL input goes high, the
phase-detect circuit again maintains lock to the
incoming NRZ data.
The TQ8103 can also be used as a standalone 622.08 MHz
frequency reference. When SEL is held low, the PLL
utilizes only the frequency-detect circuit. The PLL locks
onto the external 38.88 MHz reference to generate the
desired 622.08 MHz output.
2
For additional information and latest specifications, see our website: www.triquint.com