TCD6001 Datasheet, PDF (32/43 Pages) Tripath Technology Inc. – 6 CHANNEL CLASS-T DIGITAL AUDIO PROCESSOR USING DIGITAL POWER PROCESSINGTM TECHNOLOGY

Tripath Technology, Inc. – Preliminary Technical Information
The YSN control bit is internally XORed with the SE/BRGB pin to determine the timing of the HMUTE and
Yn/YnB outputs after automatic DC calibration. Normally, after automatic DC calibration, Yn and YnB are
held low while HMUTE is de-asserted. Then, channels begin switching one by one until all are switching.
This can help reduce startup current requirements. However, if the power stage that is being used is single
ended and has no YnB inputs because it generates its own YnB signal internally, the staggered turn-on
timing will cause the power stage outputs to be held to the negative power supply until switching begins.
This will result in a loud pop and possible speaker damage. Therefore, in this case, YSN and SE/BRGB
should be configured for immediate turn-on.
YSN
0
0
1
1
SE/BRGB
0
1
0
1
Turn-On Timing
Staggered
Immediate
Immediate
Staggered
Output Timing Control
Addr
76h
Register Name
Output Timing Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
DEL DCB DCX
0
HMF BB2 BB1 BB0
1
ext
ext
0
0
0
0
0
Control bits BB0 through BB2 are used to program a “break before make” delay in the Y outputs.
Break before make is a dead time at the Y-outputs where both Y and YB of each channel are low together
for a period of time in order to prevent shoot-through current in the output power MOSFET devices.
.
BB<2:0>
000
001
010
011
100
101
110
111
BBM Delay
0 nS
15 nS
30 nS
45 nS
60 nS
75 nS
90 nS
105 nS
Break before make (BBM) delay table
Some Tripath power stages like the TPS4070, the TPS4100, the TPD2075, and the TPD2125 handle BBM
themselves. For these and any other power stages that handle BBM on their own, TCD6001 BBM should be
set to 0 nS.
The HMF control bit, when set to ‘1’, forces the HMUTE output high regardless of the state of the system.
HMUTE operates normally when HMF is cleared to ‘0’. This function can be used to mute all power stage
outputs while the user listens to the headphone output. During automatic DC calibration the TCD6001
expects to be able to turn off both the high and low side FETs by pulling Y and Yb low. However, some
power stages like the Tripath TPD2075 and TPD2125 only have a single Y input instead of complimentary Y
and Yb inputs. When using this type of power stage, during automatic DC calibration, HMF should be set to
‘1’. This keeps the HMUTE output high during automatic DC calibration. After waiting for automatic DC
calibration to complete, HMF can be cleared to ‘0’ to resume normal switching. When using other power
stages, HMF should be kept at ‘0’.
32
TCD6001 – JL/Rev. 0.9/07.05