TMC8460 Datasheet, PDF (114/145 Pages) TRINAMIC Motion Control GmbH & Co. KG. – Integrated EtherCAT Slave Controller

TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)
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On startup, the EEPROM configuration is copied into the PDRAM, starting at address 0x0580. The address
for each register is shown in the column Configuration address (PDRAM). The configuration for a register
can be changed in this address space. If no configuration is stored in the EEPROM, the MCU or the
EtherCAT master can set the configuration.
The data to be written to the registers and the data read from the registers can be found at the
addresses given in the Memory Block x Address (PDRAM) columns. These addresses are used for EtherCAT
access. When accessing the PDRAM, the MFCIO block has the same behavior as an external MCU, so
when SyncManagers are set up on the two memory blocks, an MCU does not have access to these
regions using the PDI SPI interface.
All registers can be read at any time via the MFC CTRL SPI, if EtherCAT access for a writable register is
disabled, this register can also be written via the MFC CTRL SPI.
The register 44 (AL_STATE_OVERRIDE) has a special function and can only be accessed via MFC CTRL SPI.
Usually the outputs of the MFCIO block are only active when the EtherCAT slave is in operational state.
y ^{With this register they can be activated regardless of the EtherCAT state.}
r ^{The base addresses of the two memory blocks are fix and this portion of the PDRAM can only be used}
for MFCIO data when MFCIO registers are configured for ECAT access.
The memory blocks should be managed by SyncManagers, which must be configured separately using
the ESC’s configuration options.
a _{7.3 MFCIO Block EEPROM Parameter Map}
in ^{The configuration data for the MFCIO block registers can be stored in the I2C EEPROM to be automatically}
loaded into the ESC after power-up or after reset.
This configuration category must be the first in the EEPROM, located at address 0x0080 (word 0x40). The
category type must be 1 so that the TMC8460 loads the configuration into the memory area starting at
0x0580.
This section describes the part of the EEPROM content and XML/ESI file that is used to configure the
MFCIO block registers.
lim ^{Table 135 : EEPROM Parameter Map & ESC RAM Address Mapping for TMC8460-BI}
EEPROM Address
Function
Value
General Category Information (Values must not be changed)
0x0080:0x0081
Category Type
0x0001
e ^{0x0082:0x0083}
Category Data Size
0x002C
MFCIO Register Configuration
0x0084:0x0089
Encoder Unit Registers
r _{0x008A:0x008F}
SPI Unit Registers
0x0090:0x0095
Step/Direction Unit Registers Depends on the required configuration,
p^{0x0096:0x00A4}
PWM Unit Registers
0x00 for unused registers.
0x00A5:0x00A7 General Purpose I/O Unit Registers
See sections 7.4 for details
0x00A8:0x00A9
MFCIO IRQ Registers
0x00AA:0x00AF
MFCIO Watchdog Registers
7.4 MFCIO Register Configuration
Each register of the MFCIO block can be configured using an 8-bit EEPROM entry. Sections 7.2 and 7.3
provide information on the individual EEPROM addresses for configuring each MFCIO block register.
The following parameters and syntax are used for every MFCIO register for configuration.
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