TMPR4955B Datasheet, PDF (97/292 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 4 Memory Management System
4.1.4
32-bit Mode Address Translation
Figure 4.1.2 shows the virtual-to-physical-address translation of a 32-bit mode address. This figure
illustrates two of the possible page sizes: a 4-Kbyte page (12 bits) and a 16-Mbyte page (24 bits).
• The top portion of Figure 4.1.2 shows a virtual address with a 12-bit, or 4-Kbyte, page size,
labeled Offset. The remaining 20 bits of the address represent the VPN, and Index the 1M-entry
page table.
• The bottom portion of Figure 4.1.2 shows a virtual address with a 24-bit, or 16-Mbyte, page size,
labeled Offset. The remaining 8 bits of the address represent the VPN, and index the 256-entry
page table.
Virtual Address with 1M (2²⁰) 4-Kbyte pages
39
32 31 29 28
ASID
8
20 bits = 1 M pages
VPN
20
12 11
Bits 31, 30 and 29 of the virtual
address select user, supervisor,
or kernel address spaces.
31
Virtual-to-physical
translation in TLB
TLB
32-bit Physical Address
PFN
Virtual-to-physical
translation in TLB
TLB
0
Offset
12
Offset passed
unchanged to
physical
memory
0
Offset
Offset passed
unchanged to
physical
memory
39
32 31 29 28 24 23
0
ASID
VPN
Offset
8
8
24
8 bits = 256 pages
Virtual Address with 256 (2⁸) 16-Mbyte pages
Figure 4.1.2 32-bit Mode Virtual Address Translation
4-3