TMPR4955B Datasheet, PDF (217/292 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 11 TX4955 System Interface
11.3.9 Processor Read Request
A processor read request is issued by the following:
• driving a read command on the SysCmd bus
• driving a read address on the SysAD bus
• asserting PValid*
Only one processor read request may be pending at a time. The processor must wait for an external read
response before starting a subsequent read.
The processor moves to slave state after the issue cycle of the read request, by deasserting the PMaster*
signal. An external agent may then return the requested data through a read response. The external agent,
which is now bus master, may issue any number of writes before sending the read response data.
An example of a processor read request and an uncompelled change to slave state occurring as the read
request is issued is illustrated in Figure 11.3.16.
Cycle
MasterClock
SysAD
SysCmd
Pvalid*
PMaster*
EOK*
Master
Slave
1 2 3 4 5 6 7 8 9 10 11 12
Addr
Read
Figure 11.3.16 Processor Read Request
The TX4955 support the Read Time Out Function. This function is to detect a time out error when
response data are not returned within a certain time. See chapter 11.3.20 Mode Register of System
Interface (G2SConfig).
11.3.10 External Write Request
External write requests are similar to a processor single write except that the signal EValid* is asserted
instead of the signal PValid*. An external write request consists of the following:
• an external agent driving a write command on the SysCmd bus and a write address on the
SysAD bus
• asserting EValid* for one cycle
• driving a data identifier on the SysCmd bus and data on the SysAD bus
• asserting EValid* for one cycle.
The data identifier associated with the data cycle must contain a last data cycle indication. Note that the
external agent must gain and maintain bus mastership during these transactions (see EReq* in the Timing
Summary, earlier in this chapter).
An external write request example with the processor initially in master state is illustrated in Figure
11.3.17.
11-49