TMP86CM27FG Datasheet, PDF (95/198 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86CM27FG
When the value set in the TC7DRC is an odd number, the PPG2 pulse width is one count
longer than the PPG1 pulse width.
(b) Dead time TC7DRA:
000H ≤ TC7DRA < TC7DRC/2
To specify no dead time, set the TC7DRA to 000H.
Source clock
Counter
S,0 1
M
S/2 ^S/2+1
S/2+M
S,0 1 2 3
Dead time
M
M'
Period
PPG1 output
PPG2 output
INTTC7T
S
S
M: Dead time
Active duration
S: Period
M: Dead time
Active duration
INTTC7P
Dead time
(TC7DRA)
Dead time
(TC7DRA)
Pulse width (TC7DRC/2)
Pulse width (TC7DRC/2)
Period (TC7DRC)
Figure 8-4 Example operation in 50% duty mode:
Command and capture start, positive logic, continuous output
8.4.1.2 Variable duty mode
(1) Description
With a period specified in the TC7DRC and a pulse width in the TC7DRB, the PPG1 pin provides
a waveform having the specified pulse width while the PPG2 pin provides a waveform having a
pulse width that equals (TC7DRC – TC7DRB).
The PPG1 output is active at the beginning of a period, remains active during the pulse width spec-
ified in the TC7DRB, after which it is inactive until the end of the period. The PPG2 output is inac-
tive at the beginning of a period, remains inactive during the pulse width specified in the TC7DRB,
after which it is active until the end of the period, that is, during the pulse width of (TC7DRC –
TC7DRB).
If a dead time is specified in the TC7DRA, the pulse width (Active duration) is shortened by the
dead time.
(2) Register settings
TC7OUT = “10”, TC7DRA = “dead time”, TC7DRB = “pulse width”, TC7DRC = “period”
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