TMP86FM48 Datasheet, PDF (94/205 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86FM48
(3) Programmable divider output (PDO) mode
The programmable divider output (PDO) mode is intended to output a pulse having a
duty cycle of about 50%. The counter counts up on an internal source clock. If the timer
value matches TC5DR, the timer F/F5 is inverted, and the counter is cleared,
generating an INTTC5 interrupt. The counter keeps counting up, and the timer F/F5 is
inverted each time the timer value matches TC5DR. The P13 ( PDO5 ) pin outputs an
inversion of the timer F/F5 output level.
At a reset or when the timer stops, the timer F/F5 is cleared to “0”. So, stopping the
timer when the PDO output is low may cause the duty cycle to become smaller than the
set value.
To use the programmable divider output mode, set the output latch of the P13 port to
“1”.
Example: Output a 1024 Hz pulse (at fc = 16 MHz)
LD
(TC5CR), 00000110B
SET
(P1DR). 3
LD
(TC5DR), 3DH
LD
(TC5CR), 00100110B
; Sets PDO mode
(TC5M = 10, TC5CK = 001)
; P13 output latch ← 1
; 1/1024 ÷ 2⁷/fc ÷ 2 = 3DH
; Starts TC5
Internal clock
Up counter
01 2
n0 1 2
TC5DR
Timer F/F5
PDO5 pin output
n
Match detect
INTTC5
interrupt
n0 1 2
n0 1 2
Figure 2.10.3 PDO Mode Timing Chart
n0 1
86FM48-92
2007-08-24