TMP86FM48 Datasheet, PDF (29/205 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86FM48
• Start the IDLE0 and SLEEP0 modes
Stop (Disable) peripherals such as a timer counter.
When IDLE0 and SLEEP0 modes start, set SYSCR2<TGHALT> to “1”.
• Release the IDLE0 and SLEEP modes
IDLE0 and SLEEP0 modes include a normal release mode and an interrupt
release mode.
These modes are selected by interrupt master flag (IMF), individual interrupt
enable-flag (EF7) for INTTBT and TBTCR<TBTEN>.
After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is
automatically cleared to “0” and the operation mode is returned to the mode
preceding IDLE0 and SLEEP0 modes. Before starting the IDLE0 or SLEEP0
mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to
“1”.
When the IDLE0 and SLEEP0 modes are started with the EEPCR<ATPWDW>
= “0”, the CPU wait period for stabilizing of the power supply of Flash control
circuit is added before the operation mode is returned to the preceding modes. The
CPU wait time of IDLE0 is 2¹⁰/fc [s] and that of SLEEP0 mode is 2³/fs [s].
IDLE0 and SLEEP0 modes can also be released by inputting low level on the
RESET pin. After releasing reset, the operation mode is started from NORMAL1
mode.
Note 1: IDLE0 and SLEEP0 modes start/release without reference to
TBTCR<TBTEN> setting.
Note 2: During CPU wait, though CPU operations remain halted, but the peripheral
function operation is resumed. Therefore in this time, though the interrupt latch
might be set, interrupt operation is not executed until the CPU wait is finished.
a. Normal release mode (IMF•EF7•TBTCR<TBTEN> = “0”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which
is setting by the TBTCR<TBTCK>. After the falling edge is detected, the program
operation is resumed from the instruction following the IDLE0 and SLEEP0
modes start instruction.
b. Interrupt release mode (IMF•EF7•TBTCR<TBTEN> = “1”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which
is setting by the TBTCR<TBTCK> and INTTBT interrupt processing is started.
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed
by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might
be the shorter than the period setting by TBTCR<TBTCK>.
Note 2: When a watchdog timer interrupt is generated immediately before
IDLE0/SLEEP0 mode is started, the watchdog timer interrupt will be
processed but IDLE0/SLEEP0 mode will not be started.
86FM48-27
2007-08-24