TMP89FW24ADFG Datasheet, PDF (91/548 Pages) Toshiba Semiconductor – 8 Bit Microcontroller TLCS-870/C1 Series

TMP89FW24A
MAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the inter-
rupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/
fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 4: Bits 7 to 5 of EINTCR1 are read as "0".
External interrupt control register 2
EINTCR1
7
6
(0x00FD9) _{Bit Symbol}
-
-
Read/Write
R
R
After reset
0
0
5
4
3
2
-
INT2LVL
INT2ES
R
R
R/W
0
0
0
1
0
INT2NC
R/W
0
INI2LVL
INT2ES
INT2NC
Noise canceller pass signal level
when the interrupt request signal is
generated for external interrupt 2
0 : Initial state or signal level "L"
1 : Signal level "H"
00 : An interrupt request is generated at the rising edge of the noise cancel-
ler pass signal
Selects the interrupt request gener-
ating condition for external inter-
01 :
An interrupt request is generated at the falling edge of the noise cancel-
ler pass signal
rupt 2
10 : An interrupt request is generated at both edges of the noise canceller
pass signal
11 : Reserved
NORMAL1/2, IDLE1/2
SLOW1/2, SLEEP1
Sets the noise canceller sampling
interval for external interrupt 2
00 : fcgck [Hz]
01 : fcgck / 2² [Hz]
10 : fcgck / 2³ [Hz]
11 : fcgck / 2⁴ [Hz]
00 : fs/4 [Hz]
01 : fs/4 [Hz]
10 : fs/4 [Hz]
11 : fs/4 [Hz]
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode,
clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation
mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is
changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NOR-
MAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 3: Interrupt requests may be generated when EINTCR2 is changed. Before doing such operation, clear the correspond-
ing interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NOR-
MAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the inter-
rupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/
fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 4: Bits 7 to 5 of EINTCR2 are read as "0".
RA000
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2012/5/18