TC554161AFTI-70 Datasheet, PDF (8/10 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC554161AFTI-70,-85,-10,-70L,-85L,-10L
Note:
(1)
(2)
(3)
(4)
(5)
R/W remains HIGH for the read cycle.
If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance.
If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance.
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
DATA RETENTION CHARACTERISTICS (Ta = -40° to 85°C)
SYMBOL
PARAMETER
MIN
V_DH
Data Retention Supply Voltage
2.0
V_DH = 3.0 V
¾
-70,-85,-10
V_DH = 5.5 V
¾
I_DDS2
Standby Current
V_DH = 3.0 V
¾
-70L,-85L,-10L
V_DH = 5.5 V
¾
t_CDR
Chip Deselect to Data Retention Mode Time
0
t_R
Recovery Time
5
*: 5 mA (max) at Ta = -40° to 40°C
TYP
¾
¾
¾
¾
¾
¾
¾
MAX
5.5
100
200
50*
100
¾
¾
UNIT
V
mA
ns
ms
CE CONTROLLED DATA RETENTION MODE
V_DD
4.5 V
DATA RETENTION MODE
V_IH
CE
GND
(See Note)
t_CDR
V_DD - 0.2 V
(See Note)
t_R
Note: When CE is operating at the VIH level (2.4V), the standby current is given by IDDS1 during the transition
of VDD from 4.5 to 2.6V.
2001-08-17 8/10