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TMP86FH46BNG Datasheet, PDF (72/216 Pages) Toshiba Semiconductor – 8 Bit Microcontroller TLCS-870/C Series | |||
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6. Watchdog Timer (WDT)
6.2 Watchdog Timer Control
TMP86FH46BNG
6.2.3 Watchdog Timer Disable
To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg-
ister in other procedures causes a malfunction of the micro controller.
1. Set the interrupt master flag (IMF) to â0â.
2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to â0â.
4. Set WDTCR2 to the disable code (B1H).
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
Example :Disabling the watchdog timer
DI
LD
LDW
(WDTCR2), 04EH
(WDTCR1), 0B101H
: IMF â 0
: Clears the binary counter
: WDTEN â 0, WDTCR2 â Disable code
Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)
WDTT
00
01
10
11
DV7CK = 0
2.097
524.288 m
131.072 m
32.768 m
Watchdog Timer Detection Time[s]
NORMAL1/2 mode
DV7CK = 1
4
1
250 m
62.5 m
SLOW
mode
4
1
250 m
62.5 m
6.2.4 Watchdog Timer Interrupt (INTWDT)
When WDTCR1<WDTOUT> is cleared to â0â, a watchdog timer interrupt request (INTWDT) is gener-
ated by the binary-counter overflow.
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
master flag (IMF).
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer inter-
rupt is already accepted, the new watchdog timer interrupt is processed immediately and the previous inter-
rupt is held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of
the RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
Example :Setting watchdog timer interrupt
LD
SP, 023FH
: Sets the stack pointer
LD
(WDTCR1), 00001000B : WDTOUT â 0
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