TB31356AFL Datasheet, PDF (7/10 Pages) Toshiba Semiconductor – 1.8GHz,600MHz DUAL-PLL FREQUENCY SYNTHESIZER

TENTATIVE
TB31356AFL
l Lock detection
A signal indicating whether the PLL has phase-locked to the desired frequency is presented to the LD pin.
The PLL to be detected in this way can be selected by setting two bits, LD1 and LD2, as shown in the table
below.
LD1
LD2
Detected PLL
0
0
Not detected (fixed low)
0
1
PLL2
1
0
PLL1
1
1
Only when both PLL1 and PLL2 are
detected
Locked in phase = open, Unlocked = low, Power-down mode = open
l Power-down mode
The PLL1, PLL2, and crystal oscillator circuit can be switched between operating and power-down
modes by using three bits—SB1, SB2, and SBX. The table below shows how operation is controlled by using
these bits and external battery save pins.
External Pin
Serial Data
Operation State
BS1 BS2 SB1 SB2 SBX
PLL1
PLL2
Buffer
L
L
*
*
*
OFF
OFF
OFF
L
H
*
*
*
OFF
ON
ON
H
L
*
*
*
ON
OFF
ON
H
H
0
0
0
OFF
OFF
OFF
H
H
0
0
1
OFF
OFF
ON
H
H
0
1
*
OFF
ON
ON
H
H
1
0
*
ON
OFF
ON
H
H
1
1
*
ON
ON
ON
Notes1 : ON : operating, OFF : power-down (not operating), * : don’t care
Notes2 : Switching between operating and battery saving (power down) mode by using serial data is
renewed at the rising edge of strobe signal.
Notes3 : Switching between operating and battery saving (power down) mode by using external pin
(BS-PLL1,BS-PLL2) is controlled real-time.
Notes4 : Immediately after power on, need a initial setting by serial data before operation state “ON”.
This specification is design target. It is subject to change without notice.
Nov. 27 2002 PAGE 7