JBT6L78-AS Datasheet, PDF (7/14 Pages) Toshiba Semiconductor – Gate Driver for TFT LCD Panel

Pin Description
JBT6L78-AS
Pin Name
I/O
Function
Vertical shift data input/output pins
Input/output shift data. The pin function is switched between input and output by the U/D pin as
follows:
DI/O
DO/I
U/D
CPV
OE1 to OE3
G1 to G162
TEST1, TEST2,
TEG
V_GG
V_OFF
V_DD
V_SS
V_CC
V_EE
U/D
DI/O
DO/I
I/O
H
Input
Output
L
Output
Input
At input
Data are latched into the shift registers in sync with the rising edge of CPV.
At output:
If the JBT6L78-AS is cascade-connected, data to be input at the next stage are output from the
pin. The data state changes in sync with the falling edge of CPV.
Data transfer direction switching pin
Specifies the shift direction of the shift registers.
Data in the shift registers shift in sync with the rising edge of CPV as follows:
I
· U/D = H: G1 ® G2® G3 ® … ® G162
· U/D = L: G162 ® G161® G160 ® … ® G1
Use the pin at DC level. For High, V_DD; for Low, V_SS.
Note that if U/D mode is switched during data transfer, misoperation occurs to a display page.
I
Vertical shift clock
Shift clock for the shift registers. Data are shifted in sync with the rising edge of CPV.
Output enable pin
These pins control output data from the output pins (G1 to G162).
I
· OE = L: Normal output state (1-pulse scanning)
· OE = H: Outputs V_OFF voltage.
Note that the contents of the shift registers are not cleared. Those operations are performed
asynchronously to CPV.
O
LCD panel drive pins.
I
Test pin.
Leave the pin open.
Power supply pin for controlling LCD.
LCD off level input pin
Power supply pin for internal logic
Power supply pin for cascade output
Power supply pin for LCD control and internal logic
Power supply pin for controlling LCD
7
2001-12-21