JBT6L78-AS Datasheet, PDF (11/14 Pages) Toshiba Semiconductor – Gate Driver for TFT LCD Panel

JBT6L78-AS
Electrical Characteristics
DC Characteristics V_DD = 2.5 to 3.6 V, V_GG - V_EE = 20 to 33 V, V_OFF = V_EE to V_EE + 5 V,
V_CC = V_EE + 5 V, V_SS = 0 V, Ta = -20 to 75°C
Characteristics
Input voltage
Low level
High level
Symbol
V_IL
Test
Circuit
¾
V_IH
¾
Test Condition
¾
¾
Min
Typ.
Max
Unit
Relevant
Pin
0
¾
V_DD ´
0.2
V
V_DD ´
0.8
¾
V_DD
(Note 1)
Output
voltage
Low level
High level
Input leakage current
Output resistance
Current dissipation (1)
Current dissipation (2)
Current dissipation (3)
Current dissipation (4)
Current dissipation (5)
V_OL
V_OH
I_IN
R_OL
R_OH
I_GG
I_DD
I_CC
I_OFF
I_EE
¾ I_OL = 100 mA
¾
¾
¾ I_OH = -100 mA
¾
¾
V_DD -
0.4
¾
¾
¾
¾ V_OFF level output
¾ V_GG level output
¾
¾
¾
¾
¾
¾
¾
¾
¾
(Note 2) ¾
¾
¾
¾
¾
¾
-400 ¾
0.4
V
¾
1.0 mA
1.0 kW
50
mA
500 mA
80
mA
40
mA
¾
mA
DI/O,
DO/I
G1 to
G162
Note 1: DI/O, DO/I, CPV, OE1 to OE3
Note 2: No load, CPV = 21 kHz, DI/O input cycle = 60 Hz, V_DD = 3.6 V, V_EE = -15 V,
CPV High width = 23.8 ms, 1-clock cycle DI/O input, OE1 to OE3 = Low, U/D = High
AC Characteristics V_DD = 2.5 to 3.6 V, V_GG - V_EE = 20 to 33 V, V_OFF = V_EE to V_EE + 5 V,
V_CC = V_EE + 5 V, V_SS = 0 V, Ta = -20 to 75°C
Characteristics
Clock pulse width (H)
Clock pulse width (L)
Data setup time
Data hold time
Output delay time (1)
Output delay time (2)
Output delay time (3)
Symbol
t_CPVH
t_CPVL
t_sDI
t_hDI
t_pdDO
t_pdG
t_pdOE
Test
Circuit
Test Condition
¾
¾
¾
¾
¾
¾
¾
¾
¾ C_L = 20 pF
¾ C_L = 100 pF
¾ C_L = 100 pF
Min Max Unit
10
¾
ms
10
¾
ms
1
¾
ms
1
¾
ms
¾
1
ms
¾
2
ms
¾
2
ms
11
2001-12-21