TMP86P820FG Datasheet, PDF (61/170 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86P820FG
4. Special Function Register (SFR)
The TMP86P820FG adopts the memory mapped I/O system, and all peripheral control and data transfers are per-
formed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address
0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for
TMP86P820FG.
4.1 SFR
Address
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
0010H
0011H
0012H
0013H
0014H
0015H
0016H
0017H
0018H
0019H
001AH
001BH
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
0024H
0025H
Read
P1PRD
P2PRD
P3PRD
P5PRD
P7PRD
TC1SR
ADCDR1
ADCDR2
Reserved
P1DR
P2DR
P3DR
P3OUTCR
P5DR
P6DR
P7DR
P6CR
ADCCR1
ADCCR2
TREG1AL
TREG1AM
TREG1AH
TREG1B
TC1CR1
TC1CR2
Reserved
TC3CR
TC4CR
Reserved
Reserved
TTREG3
TTREG4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Page 47
Write
-
-
-
-
-
-
-
-