TMP86FS49AUG Datasheet, PDF (51/294 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86FS49AUG
3. Interrupt Control Circuit
The TMP86FS49AUG has a total of 24 interrupt sources excluding reset. Interrupts can be nested with priorities.
Four of the internal interrupt sources are non-maskable while the rest are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its inter-
rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi-
nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Internal/External
Internal
Internal
Internal
Internal
External
Internal
External
Internal
External
Internal
Internal
Internal
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
External
Interrupt Factors
Enable Condition
(Reset)
INTSWI (Software interrupt)
INTUNDEF (Executed the undefined instruction
interrupt)
INTATRAP (Address trap interrupt)
INTWDT (Watchdog timer interrupt)
INT0
INTTC1
INT1
INTTBT
INT2
INTTC4
INTTC3
INTSBI
INT3
INTSIO1
INTSIO2
INTADC
INTRXD1
INTTXD1
INTTC6
INTTC5
INTRXD2
INTTXD2
INTTC2
INT5
Non-maskable
Non-maskable
Non-maskable
Non-maskable
Non-maskable
IMF• EF4 = 1, INT0EN = 1
IMF• EF5 = 1
IMF• EF6 = 1
IMF• EF7 = 1
IMF• EF8 = 1
IMF• EF9 = 1
IMF• EF10 = 1
IMF• EF11 = 1
IMF• EF12 = 1
IMF• EF13 = 1
IMF• EF14 = 1
IMF• EF15 = 1
IMF• EF16 = 1
IMF• EF17 = 1
IMF• EF18 = 1
IMF• EF19 = 1
IMF• EF20 = 1
IMF• EF21 = 1
IMF• EF22 = 1
IMF• EF23 = 1
Interrupt
Latch
–
–
–
IL2
IL3
IL4
IL5
IL6
IL7
IL8
IL9
IL10
IL11
IL12
IL13
IL14
IL15
IL16
IL17
IL18
IL19
IL20
IL21
IL22
IL23
Vector
Address
FFFE
FFFC
FFFC
FFFA
FFF8
FFF6
FFF4
FFF2
FFF0
FFEE
FFEC
FFEA
FFE8
FFE6
FFE4
FFE2
FFE0
FFBE
FFBC
FFBA
FFB8
FFB6
FFB4
FFB2
FFB0
Priority
1
2
2
2
2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is
cancelled). For details, see “Address Trap”.
Note 2: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
Note 3: If an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15 (INTADC) is
being accepted, the INTADC interrupt latch may be cleared without the INTADC interrupt being processed. For details,
refer to the corresponding notes in the chapter on the AD converter.
3.1 Interrupt latches (IL23 to IL2)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to “0” during reset.
Page 35