TMP86FS49AUG Datasheet, PDF (201/294 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86FS49AUG
SIO2CR<SIOS>
Writing transmit data
Clearing SIOS
SIO2SR<SIOF>
SIO2SR<SEF>
SCK2 pin
Start shift
operation
Start shift
operation
Start shift
operation
SO2 pin
SIO2SR<TXF>
INTSIO2
interrupt
request
SIO2TDB <SIOS>
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
A
B
C
Writing transmit Writing transmit
data A
data B
Writing transmit
data C
Figure 15-7 Exaple of External Clock and MSB Transmit Mode
SCK2 pin
SIO2SR<SIOF>
SO2 pin
tSODH
4/fc < ^tSODH < 8/fc
Figure 15-8 Hold Time of the End of Transmit Mode
(4) Transmit error processing
Transmit errors occur on the following situation.
• Shift operation starts before writing next transmit data to SIO2TDB in external clock opera-
tion.
If transmit errors occur during transmit operation, SIO2SR<TXERR> is set to “1” immedi-
ately after starting shift operation. Synchronizing with the next serial clock falling edge,
INTSIO2 interrupt request is generated.
If shift operation starts before writing data to SIO2TDB after SIO2CR<SIOS> is set to “1”,
SIO2SR<TXERR> is set to “1” immediately after shift operation is started and then
INTSIO2 interrupt request is generated.
SIO2 pin is kept in high level when SIO2SR<TXERR> is set to “1”. When transmit error
occurs, transmit operation must be forcibly stop by writing SIO2CR<SIOINH> to “1”. In
this case, SIO2CR<SIOS>, SIO2SR register, SIO2RDB register and SIO2TDB register are
initialized.
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