TLP113 Datasheet, PDF (5/8 Pages) Toshiba Semiconductor – Isolated Line Receiver Simplex / Multiplex Data Transmission Computer.Peripheral Interface Microprocessor System Interface Digital Isolation For A / D

Test Circuit 1: Switching Time Test Circuit
Pulse input
PW = 100µs
Duty ratio = 1 / 10
IF monitor
VCC
GND
VCC = 5V
IF
CL
VO
Output
monitor
VO
tf
tpHL
16mA
8mA
0mA
tr
5V4.5V
1.5V
0.5V
tpLH
VOL
C_L is approximately 15pF which includes probe and stray wiring capacitance.
Test Circuit 2: Common Mode Transient Immunity Test Circuit
IF
VCC
GND
VCM
Pulse gen
ZO = 50Ω
VCC = 5V
VCM
CL
VO
Output
tr
monitor _{(IF =V0OmA)}
(IF = ^V10OmA)
90%
200V
10%
tf
0V
5V
2V
0.8V
VOL
CΜΗ
=
160(V)
tr (µs)
,
CΜ_L
=
160(V)
tf (µs)
C_L is approximately 15pF which includes probe and stray wiring capacitance.
TLP113
5
2002-09-25